333 lines
9.6 KiB
Verilog
333 lines
9.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9963 #(
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// parameters
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter ADC_IODELAY_ENABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter IODELAY_ENABLE = 0,
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parameter DAC_DDS_TYPE = 1,
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parameter DAC_DDS_CORDIC_DW = 14,
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parameter DAC_DDS_CORDIC_PHASE_DW = 13,
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parameter DAC_DATAPATH_DISABLE = 0,
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parameter ADC_USERPORTS_DISABLE = 0,
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parameter ADC_DATAFORMAT_DISABLE = 0,
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parameter ADC_DCFILTER_DISABLE = 0,
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parameter ADC_IQCORRECTION_DISABLE = 0,
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parameter ADC_SCALECORRECTION_ONLY = 1,
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parameter DELAY_REFCLK_FREQUENCY = 200) (
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// physical interface (receive)
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input trx_clk,
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input trx_iq,
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input [11:0] trx_data,
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// physical interface (transmit)
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input tx_clk,
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output tx_iq,
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output [11:0] tx_data,
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// transmit master/slave
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input dac_sync_in,
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output dac_sync_out,
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// delay clock
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input delay_clk,
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// master interface
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output adc_clk,
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output dac_clk,
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output adc_rst,
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output dac_rst,
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// dma interface
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output adc_enable_i,
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output adc_valid_i,
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output [15:0] adc_data_i,
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output adc_enable_q,
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output adc_valid_q,
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output [15:0] adc_data_q,
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input adc_dovf,
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output dac_enable_i,
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output dac_valid_i,
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input [15:0] dac_data_i,
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output dac_enable_q,
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output dac_valid_q,
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input [15:0] dac_data_q,
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input dac_dunf,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal registers
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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// internal clocks and resets
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wire up_clk;
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wire up_rstn;
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wire delay_rst;
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// internal signals
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wire adc_valid_s;
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wire [23:0] adc_data_s;
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wire adc_status_s;
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wire dac_valid_s;
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wire [23:0] dac_data_s;
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wire [12:0] up_adc_dld_s;
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wire [64:0] up_adc_dwdata_s;
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wire [64:0] up_adc_drdata_s;
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wire delay_locked_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_rx_s;
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wire up_wack_tx_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_rx_s;
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wire up_rack_rx_s;
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wire [31:0] up_rdata_tx_s;
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wire up_rack_tx_s;
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wire up_adc_ce;
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wire up_dac_ce;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// processor read interface
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always @(*) begin
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up_wack = up_wack_rx_s | up_wack_tx_s;
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up_rack = up_rack_rx_s | up_rack_tx_s;
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up_rdata = up_rdata_rx_s | up_rdata_tx_s;
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end
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// device interface
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axi_ad9963_if #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
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.IO_DELAY_GROUP (IO_DELAY_GROUP),
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.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
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i_dev_if (
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.trx_clk (trx_clk),
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.trx_iq (trx_iq),
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.trx_data (trx_data),
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.tx_clk (tx_clk),
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.tx_iq (tx_iq),
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.tx_data (tx_data),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s),
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.adc_status (adc_status_s),
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.up_adc_ce(up_adc_ce),
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.dac_valid (dac_valid_s),
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.dac_data (dac_data_s),
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.up_dac_ce(up_dac_ce),
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.up_clk (up_clk),
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.up_adc_dld (up_adc_dld_s),
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.up_adc_dwdata (up_adc_dwdata_s),
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.up_adc_drdata (up_adc_drdata_s),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked_s));
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// receive
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axi_ad9963_rx #(
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.ID (ID),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE),
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.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE),
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.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE),
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.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE),
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.SCALECORRECTION_ONLY (ADC_SCALECORRECTION_ONLY),
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.IODELAY_ENABLE (ADC_IODELAY_ENABLE)
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) i_rx (
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.adc_rst (adc_rst),
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.adc_clk (adc_clk),
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s),
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.adc_status (adc_status_s),
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.up_adc_ce(up_adc_ce),
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.up_dld (up_adc_dld_s),
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.up_dwdata (up_adc_dwdata_s),
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.up_drdata (up_adc_drdata_s),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked_s),
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.adc_enable_i (adc_enable_i),
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.adc_valid_i (adc_valid_i),
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.adc_data_i (adc_data_i),
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.adc_enable_q (adc_enable_q),
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.adc_valid_q (adc_valid_q),
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.adc_data_q (adc_data_q),
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.adc_dovf (adc_dovf),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_rx_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_rx_s),
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.up_rack (up_rack_rx_s));
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// transmit
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axi_ad9963_tx #(
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.ID (ID),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.DAC_DDS_TYPE (DAC_DDS_TYPE),
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.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
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.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
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.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
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i_tx (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_valid (dac_valid_s),
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.dac_data (dac_data_s),
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.adc_data (adc_data_s),
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.dac_sync_in (dac_sync_in),
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.dac_sync_out (dac_sync_out),
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.dac_enable_i (dac_enable_i),
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.dac_valid_i (dac_valid_i),
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.dac_data_i (dac_data_i),
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.dac_enable_q (dac_enable_q),
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.dac_valid_q (dac_valid_q),
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.dac_data_q (dac_data_q),
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.dac_dunf(dac_dunf),
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.up_dac_ce(up_dac_ce),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_tx_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_tx_s),
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.up_rack (up_rack_tx_s));
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// axi interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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