pluto_hdl_adi/library/axi_dmac
Laszlo Nagy 1f1b2b4fa3 axi_dmac:axi_dmac_ip: Fix AXI Stream signals bundle
The unused AXI stream signals have to be added to the AXIS interface so
they don't hang loose on the IP in the block design.
2019-07-08 16:08:06 +03:00
..
bd axi_dmac: patch version checking 2018-12-20 10:32:48 +02:00
tb tb_base: Fix various test benches 2019-05-17 11:20:48 +03:00
2d_transfer.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
Makefile all: Rename altera to intel 2019-06-29 06:53:51 +03:00
address_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac.v axi_dmac: bundle AXI Stream signals into bus for Intel 2019-05-16 13:27:19 +03:00
axi_dmac_burst_memory.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
axi_dmac_constr.sdc axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_constr.ttcl axi_dmac: early abort support 2018-09-07 11:38:04 +03:00
axi_dmac_hw.tcl scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
axi_dmac_ip.tcl axi_dmac:axi_dmac_ip: Fix AXI Stream signals bundle 2019-07-08 16:08:06 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v axi_dmac: version bump for minor patches 2019-05-24 11:11:08 +03:00
axi_dmac_regmap_request.v axi_dmac: clear measured transfer length when core disabled 2019-05-24 11:11:08 +03:00
axi_dmac_reset_manager.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
axi_dmac_resize_dest.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_resize_src.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_response_manager.v whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
axi_dmac_transfer.v axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
axi_register_slice.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
data_mover.v axi_dmac: patch xfer_request 2019-05-24 11:11:08 +03:00
dest_axi_mm.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
dest_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v axi_dmac: patch for partial 2D transfer support 2019-05-24 11:11:08 +03:00
request_generator.v whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
response_handler.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
splitter.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_mm.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
src_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00