21 lines
448 B
Tcl
21 lines
448 B
Tcl
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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# System clock is 100 MHz for this base design
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set sys_cpu_clk_freq 100
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# ADC external clock generator configurations, the reference clock is the
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# system clock
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# NOTE: For '7 Series' FPGAs the FVCO must be between 600 MHz and 12000 MHz
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set clkgen_vco_div 5
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set clkgen_vco_mul 50
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# specify the external clock rate in MHz (MCLKIN)
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set ext_clk_rate 25
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source ../common/ad7405_bd.tcl
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