106 lines
5.1 KiB
Verilog
106 lines
5.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns / 1ps
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module axi_ad9162_if #(
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parameter DEVICE_TYPE = 0) (
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// jesd interface
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// tx_clk is (line-rate/40)
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input tx_clk,
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output reg [255:0] tx_data,
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// dac interface
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output dac_clk,
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input dac_rst,
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input [255:0] dac_data);
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// internal registers
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// reorder data for the jesd links
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assign dac_clk = tx_clk;
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always @(posedge tx_clk) begin
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tx_data[255:248] <= (DEVICE_TYPE == 1) ? dac_data[ 55: 48] : dac_data[247:240];
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tx_data[247:240] <= (DEVICE_TYPE == 1) ? dac_data[119:112] : dac_data[183:176];
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tx_data[239:232] <= (DEVICE_TYPE == 1) ? dac_data[183:176] : dac_data[119:112];
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tx_data[231:224] <= (DEVICE_TYPE == 1) ? dac_data[247:240] : dac_data[ 55: 48];
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tx_data[223:216] <= (DEVICE_TYPE == 1) ? dac_data[ 63: 56] : dac_data[255:248];
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tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data[127:120] : dac_data[191:184];
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tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data[191:184] : dac_data[127:120];
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tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data[255:248] : dac_data[ 63: 56];
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tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data[ 39: 32] : dac_data[231:224];
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tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data[103: 96] : dac_data[167:160];
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tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data[167:160] : dac_data[103: 96];
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tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data[231:224] : dac_data[ 39: 32];
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tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data[ 47: 40] : dac_data[239:232];
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tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data[111:104] : dac_data[175:168];
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tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data[175:168] : dac_data[111:104];
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tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data[239:232] : dac_data[ 47: 40];
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tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data[ 23: 16] : dac_data[215:208];
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tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data[ 87: 80] : dac_data[151:144];
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tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data[151:144] : dac_data[ 87: 80];
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tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data[215:208] : dac_data[ 23: 16];
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tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data[ 31: 24] : dac_data[223:216];
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tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data[ 95: 88] : dac_data[159:152];
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tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data[159:152] : dac_data[ 95: 88];
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tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data[223:216] : dac_data[ 31: 24];
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tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data[ 7: 0] : dac_data[199:192];
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tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data[ 71: 64] : dac_data[135:128];
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tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data[135:128] : dac_data[ 71: 64];
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tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data[199:192] : dac_data[ 7: 0];
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tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data[ 15: 8] : dac_data[207:200];
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tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data[ 79: 72] : dac_data[143:136];
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tx_data[ 15: 8] <= (DEVICE_TYPE == 1) ? dac_data[143:136] : dac_data[ 79: 72];
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tx_data[ 7: 0] <= (DEVICE_TYPE == 1) ? dac_data[207:200] : dac_data[ 15: 8];
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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