121 lines
5.3 KiB
Tcl
Executable File
121 lines
5.3 KiB
Tcl
Executable File
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package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME axi_ad9250
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set_module_property DESCRIPTION "AXI AD9250 Interface"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_ad9250
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL axi_ad9250
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add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
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add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
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add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
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add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
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add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
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add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
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add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
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add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
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add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
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add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
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add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
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add_fileset_file axi_ad9250_pnmon.v VERILOG PATH axi_ad9250_pnmon.v
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add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v
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add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v
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add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v TOP_LEVEL_FILE
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add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
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add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
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add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
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add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID TYPE INTEGER
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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add_parameter DEVICE_TYPE INTEGER 0
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set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
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set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
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set_parameter_property DEVICE_TYPE TYPE INTEGER
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set_parameter_property DEVICE_TYPE UNITS None
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set_parameter_property DEVICE_TYPE HDL_PARAMETER true
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# axi4 slave
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add_interface s_axi_clock clock end
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add_interface_port s_axi_clock s_axi_aclk clk Input 1
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add_interface s_axi_reset reset end
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set_interface_property s_axi_reset associatedClock s_axi_clock
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add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
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add_interface s_axi axi4lite end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input 16
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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add_interface_port s_axi s_axi_wdata wdata Input 32
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add_interface_port s_axi s_axi_wstrb wstrb Input 4
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add_interface_port s_axi s_axi_wready wready Output 1
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add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input 16
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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# transceiver interface
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ad_alt_intf clock rx_clk input 1
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ad_alt_intf signal rx_sof input 4 export
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add_interface if_rx_data avalon_streaming sink
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add_interface_port if_rx_data rx_data data input 64
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add_interface_port if_rx_data rx_valid valid input 1
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add_interface_port if_rx_data rx_ready ready output 1
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set_interface_property if_rx_data associatedClock if_rx_clk
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set_interface_property if_rx_data dataBitsPerSymbol 64
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# dma interface
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ad_alt_intf clock adc_clk output 1
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ad_alt_intf reset adc_rst output 1 if_adc_clk
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add_interface adc_ch_0 conduit end
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add_interface_port adc_ch_0 adc_enable_a enable Output 1
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add_interface_port adc_ch_0 adc_valid_a valid Output 1
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add_interface_port adc_ch_0 adc_data_a data Output 32
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set_interface_property adc_ch_0 associatedClock if_rx_clk
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set_interface_property adc_ch_0 associatedReset none
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add_interface adc_ch_1 conduit end
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add_interface_port adc_ch_1 adc_enable_b enable Output 1
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add_interface_port adc_ch_1 adc_valid_b valid Output 1
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add_interface_port adc_ch_1 adc_data_b data Output 32
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set_interface_property adc_ch_1 associatedClock if_rx_clk
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set_interface_property adc_ch_1 associatedReset none
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ad_alt_intf signal adc_dovf input 1 ovf
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ad_alt_intf signal adc_dunf input 1 unf
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