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Lars-Peter Clausen 1202286c3d Add ADI JESD204 link layer cores 
The ADI JESD204 link layer cores are a implementation of the JESD204 link
layer. They are responsible for handling the control signals (like SYNC and
SYSREF) and controlling the link state machine as well as performing
per-lane (de-)scrambling and character replacement.

Architecturally the cores are separated into two components.

1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take
care of the JESD204 protocol handling. They have configuration and status
ports that allows to configure their behaviour and monitor the current
state. The processing cores run entirely in the lane_rate/40 clock domain.

They have a upstream and a downstream port that accept and generate raw PHY
level data and transport level payload data (which is which depends on the
direction of the core).

2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The
configuration interface cores provide a register map interface that allow
access to the to the configuration and status interfaces of the processing
cores. The configuration cores are responsible for implementing the clock
domain crossing between the lane_rate/40 and register map clock domain.

These new cores are compatible to all ADI converter products using the
JESD204 interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-05-23 11:16:07 +02:00
..
altera alt_mul- qsys replacement 2017-05-18 10:38:48 -04:00
axi_ad5766 Create CDC helper library 2017-05-23 11:16:07 +02:00
axi_ad6676 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad7616 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9122 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9144 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9152 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9162 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9234 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9250 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9265 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9361 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9371 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9434 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9467 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9625 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9643 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9652 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9671 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9680 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9684 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9739a all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_ad9963 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_adc_decimate all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_adc_trigger all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_clkgen all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_dac_interpolate all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_dmac Create CDC helper library 2017-05-23 11:16:07 +02:00
axi_fmcadc5_sync all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_generic_adc all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_gpreg all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_hdmi_rx axi_hdmi_rx- move data to an iob 2017-05-19 16:25:54 -04:00
axi_hdmi_tx all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_i2s_adi license: Fix VHDL license header 2017-05-17 18:28:06 +03:00
axi_intr_monitor all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_logic_analyzer all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_mc_controller all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_mc_current_monitor all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_mc_speed all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_rd_wr_combiner all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_spdif_rx license: Fix VHDL license header 2017-05-17 18:28:06 +03:00
axi_spdif_tx Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
axi_usb_fx3 axi_usb_fx3: Add missing ports 2017-05-17 14:48:28 +03:00
cn0363 all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
common Create CDC helper library 2017-05-23 11:16:07 +02:00
cordic_demod all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
interfaces interfaces: Add dependencies to rule 2017-05-23 11:16:07 +02:00
jesd204 Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
prcfg all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
scripts adi_ip.pl: adi_ip_properties_lite: Set core name to the specified name 2017-05-23 11:16:07 +02:00
spi_engine Create CDC helper library 2017-05-23 11:16:07 +02:00
util_adcfifo resolving conflicts 2017-05-17 16:18:53 -04:00
util_axis_fifo Create CDC helper library 2017-05-23 11:16:07 +02:00
util_axis_resize all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_bsplit all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_ccat all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_cdc util_cdc: Add multi-bit data synchronization module 2017-05-23 11:16:07 +02:00
util_cic all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_clkdiv all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_cpack all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_dacfifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_extract all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_fir_dec all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_fir_int all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_gmii_to_rgmii all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_i2c_mixer Fix VHDL files license header, second try 2017-05-17 15:25:08 +02:00
util_mfifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_pmod_adc all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_pmod_fmeter all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_pulse_gen util_pulse_gen: Add Makefile 2017-04-27 11:28:25 +03:00
util_rfifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_sigma_delta_spi all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_tdd_sync all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_upack all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_var_fifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
util_wfifo all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
xilinx adi_ip.tcl: Use analog.com for interface vendor 2017-05-23 11:16:07 +02:00
Makefile Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00