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pluto_hdl_adi/library/axi_dmac
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Mathias Tausen cd04141ffd axi_dmac: Add parameter controlling AWCACHE 
On architectures with ports that support cache coherency, the AWCACHE
signal must be set to indicate that transactions are cached. This patch
adds a parameter allowing AWCACHE to be set on an AXI4 destination port.
 		2022-05-10 11:50:55 +03:00
..
bd axi_dmac: generalize version check 2020-04-03 11:18:59 +03:00
tb library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer 2022-04-01 16:02:46 +03:00
Makefile library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer 2022-04-01 16:02:46 +03:00
address_generator.v axi_dmac: Add parameter controlling AWCACHE 2022-05-10 11:50:55 +03:00
axi_dmac.v axi_dmac: Add parameter controlling AWCACHE 2022-05-10 11:50:55 +03:00
axi_dmac_burst_memory.v axi_dmac: fix non-blocking assignment in combinatorial block 2021-03-01 09:21:59 +02:00
axi_dmac_constr.sdc axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_constr.ttcl axi_dmac: Update IP with the new util_axis_fifo 2020-12-04 11:00:53 +02:00
axi_dmac_hw.tcl library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer 2022-04-01 16:02:46 +03:00
axi_dmac_ip.tcl axi_dmac: Add parameter controlling AWCACHE 2022-05-10 11:50:55 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v axi_dmac: Add parameter controlling AWCACHE 2022-05-10 11:50:55 +03:00
axi_dmac_regmap_request.v axi_dmac: Restore axi_dmac_regmap_request to f7b8a2d version 2021-07-02 15:52:48 +03:00
axi_dmac_reset_manager.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
axi_dmac_resize_dest.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_resize_src.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_response_manager.v axi_dmac: Update IP with the new util_axis_fifo 2020-12-04 11:00:53 +02:00
axi_dmac_transfer.v axi_dmac: Add parameter controlling AWCACHE 2022-05-10 11:50:55 +03:00
axi_register_slice.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
data_mover.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
dest_axi_mm.v axi_dmac: Add parameter controlling AWCACHE 2022-05-10 11:50:55 +03:00
dest_axi_stream.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
dest_fifo_inf.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
dmac_2d_transfer.v library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer 2022-04-01 16:02:46 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v axi_dmac: Add parameter controlling AWCACHE 2022-05-10 11:50:55 +03:00
request_generator.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
response_handler.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
splitter.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_mm.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
src_axi_stream.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
src_fifo_inf.v libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00