356 lines
10 KiB
Verilog
356 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns / 1ps
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module axi_ad777x #(
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parameter ID = 0
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) (
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input adc_dovf,
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input clk_in,
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input ready_in,
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output sync_adc_mosi,
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input sync_adc_miso,
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input [ 3:0] data_in,
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output adc_enable_0,
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output adc_enable_1,
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output adc_enable_2,
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output adc_enable_3,
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output adc_enable_4,
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output adc_enable_5,
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output adc_enable_6,
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output adc_enable_7,
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output adc_valid_0,
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output adc_valid_1,
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output adc_valid_2,
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output adc_valid_3,
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output adc_valid_4,
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output adc_valid_5,
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output adc_valid_6,
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output adc_valid_7,
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output [31:0] adc_data_0,
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output [31:0] adc_data_1,
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output [31:0] adc_data_2,
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output [31:0] adc_data_3,
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output [31:0] adc_data_4,
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output [31:0] adc_data_5,
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output [31:0] adc_data_6,
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output [31:0] adc_data_7,
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output adc_clk,
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output adc_reset,
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output adc_valid,
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output [ 7:0] adc_crc_ch_mismatch,
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready
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);
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// internal registers
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reg [31:0] up_rdata = 'd0;
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reg up_rack = 'd0;
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reg up_wack = 'd0;
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reg [31:0] up_rdata_r;
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reg up_rack_r;
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reg up_wack_r;
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// internal signals
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wire adc_rst_s;
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wire up_rstn;
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wire up_clk;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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wire adc_clk_s;
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wire up_wreq_s;
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wire up_rreq_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s[0:8];
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wire [8:0] up_rack_s;
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wire [8:0] up_wack_s;
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wire [7:0] adc_enable;
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wire [4:0] adc_num_lanes;
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wire adc_crc_enable;
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wire [7:0] adc_status_header[0:7];
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wire [7:0] adc_crc_err;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign adc_clk = adc_clk_s;
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assign adc_reset = adc_rst_s;
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assign adc_enable_0 = adc_enable[0];
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assign adc_enable_1 = adc_enable[1];
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assign adc_enable_2 = adc_enable[2];
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assign adc_enable_3 = adc_enable[3];
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assign adc_enable_4 = adc_enable[4];
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assign adc_enable_5 = adc_enable[5];
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assign adc_enable_6 = adc_enable[6];
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assign adc_enable_7 = adc_enable[7];
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assign adc_valid_0 = adc_valid;
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assign adc_valid_1 = adc_valid;
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assign adc_valid_2 = adc_valid;
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assign adc_valid_3 = adc_valid;
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assign adc_valid_4 = adc_valid;
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assign adc_valid_5 = adc_valid;
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assign adc_valid_6 = adc_valid;
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assign adc_valid_7 = adc_valid;
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assign adc_crc_ch_mismatch = adc_crc_err;
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integer j;
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always @(*) begin
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up_rdata_r = 'h00;
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up_rack_r = 'h00;
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up_wack_r = 'h00;
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for (j = 0; j <= 8; j=j+1) begin
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up_rack_r = up_rack_r | up_rack_s[j];
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up_wack_r = up_wack_r | up_wack_s[j];
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up_rdata_r = up_rdata_r | up_rdata_s[j];
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_rdata <= up_rdata_r;
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up_rack <= up_rack_r;
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up_wack <= up_wack_r;
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end
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end
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// adc channels
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generate
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genvar i;
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for (i = 0; i < 8; i=i+1) begin : ad777x_channels
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up_adc_channel #(
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.CHANNEL_ID(i)
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) i_up_adc_channel (
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.adc_clk (adc_clk_s),
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.adc_rst (adc_rst_s),
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.adc_enable (adc_enable[i]),
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.adc_iqcor_enb (),
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.adc_dcfilt_enb (),
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.adc_dfmt_se (),
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.adc_dfmt_type (),
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.adc_dfmt_enable (),
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.adc_dcfilt_offset (),
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.adc_dcfilt_coeff (),
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.adc_iqcor_coeff_1 (),
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.adc_iqcor_coeff_2 (),
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.adc_pnseq_sel (),
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.adc_data_sel (),
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.adc_pn_err (1'b0),
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.adc_pn_oos (1'b0),
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.adc_or (1'b0),
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.adc_status_header(adc_status_header[i]),
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.adc_crc_err(adc_crc_err[i]),
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.up_adc_pn_err (),
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.up_adc_pn_oos (),
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.up_adc_or (),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd32),
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.adc_usr_datatype_bits (8'd32),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[i]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[i]),
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.up_rack (up_rack_s[i]));
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end
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endgenerate
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// adc interface
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axi_ad777x_if i_ad777x_if (
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.clk_in (clk_in),
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.ready_in (ready_in),
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.data_in (data_in),
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.adc_clk (adc_clk_s),
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.adc_valid (adc_valid),
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.sync_adc_mosi(sync_adc_mosi),
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.sync_adc_miso(sync_adc_miso),
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.adc_crc_ch_mismatch(adc_crc_err),
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.adc_num_lanes(adc_num_lanes),
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.adc_crc_enable(adc_crc_enable),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_data_2 (adc_data_2),
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.adc_data_3 (adc_data_3),
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.adc_data_4 (adc_data_4),
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.adc_data_5 (adc_data_5),
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.adc_data_6 (adc_data_6),
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.adc_data_7 (adc_data_7),
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.adc_status_0(adc_status_header[0]),
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.adc_status_1(adc_status_header[1]),
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.adc_status_2(adc_status_header[2]),
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.adc_status_3(adc_status_header[3]),
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.adc_status_4(adc_status_header[4]),
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.adc_status_5(adc_status_header[5]),
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.adc_status_6(adc_status_header[6]),
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.adc_status_7(adc_status_header[7]));
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// adc up common
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up_adc_common #(
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.ID(ID)
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) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk_s),
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.adc_rst (adc_rst_s),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status ('h00),
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.adc_sync_status (1'b1),
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.adc_status_ovf (adc_dovf),
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.adc_clk_ratio (32'd1),
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.adc_start_code (),
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.adc_sref_sync (),
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.adc_sync (),
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.adc_ext_sync_arm(),
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.adc_ext_sync_disarm(),
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.adc_ext_sync_manual_req(),
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.adc_custom_control(),
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.adc_sdr_ddr_n(),
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.adc_symb_op(),
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.adc_symb_8_16b(),
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.adc_num_lanes(adc_num_lanes),
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.adc_crc_enable(adc_crc_enable),
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.up_pps_rcounter (32'b0),
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.up_pps_status (1'b0),
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.up_pps_irq_mask (),
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.up_adc_ce (),
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.up_status_pn_err (1'b0),
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.up_status_pn_oos (1'b0),
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.up_status_or (1'b0),
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.up_adc_r1_mode(),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (32'd0),
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.up_drp_ready (1'd0),
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.up_drp_locked (1'd1),
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.up_usr_chanmax_out (),
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.up_usr_chanmax_in (8),
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.up_adc_gpio_in (32'b0),
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.up_adc_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[8]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[8]),
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.up_rack (up_rack_s[8]));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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