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Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints 
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
 		2014-03-31 17:38:20 +03:00
library dds output is reset if disabled 2014-03-31 10:01:49 -04:00
projects base_design: Fixed AC701 and VC707 contstraints 2014-03-31 17:38:20 +03:00
.gitignore added gitignore 2014-03-05 10:47:16 -05:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Update README.md 2014-03-13 14:03:15 -04:00

README.md

hdl

Analog Devices HDL libraries and projects

http://wiki.analog.com/resources/fpga/docs/hdl/github

http://wiki.analog.com/resources/fpga/docs/hdl/regmap