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Lars-Peter Clausen a9c6148570 fmcomms6: Better cope with higher sample rates There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2014-12-04 13:56:59 +01:00
library	up_axi: Fix up_raddr/up_waddr port width	2014-12-01 13:22:28 +01:00
projects	fmcomms6: Better cope with higher sample rates	2014-12-04 13:56:59 +01:00
.gitignore	a5soc: increase pipeline for qsys	2014-05-04 10:38:53 -04:00
LICENSE	Update LICENSE	2014-03-11 15:06:52 -04:00
README.md	Add a link to EngineerZone	2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga