518 lines
14 KiB
Verilog
518 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_gt_channel_1 (
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// channel interface (pll)
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cpll_rst_m,
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cpll_ref_clk_in,
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qpll_ref_clk,
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qpll_locked,
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qpll_clk,
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// channel interface (rx)
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rx_p,
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rx_n,
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rx_out_clk,
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rx_clk,
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rx_rst,
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rx_rst_m,
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rx_sof,
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rx_data,
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rx_sysref,
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rx_sync,
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rx_pll_rst,
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rx_gt_rst,
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rx_gt_rst_m,
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rx_gt_charisk,
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rx_gt_disperr,
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rx_gt_notintable,
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rx_gt_data,
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rx_gt_comma_align_enb,
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rx_gt_ilas_f,
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rx_gt_ilas_q,
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rx_gt_ilas_a,
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rx_gt_ilas_r,
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rx_gt_cgs_k,
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rx_ip_rst,
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rx_ip_sof,
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rx_ip_data,
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rx_ip_sysref,
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rx_ip_sync,
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rx_ip_rst_done,
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rx_pll_locked,
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rx_user_ready,
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rx_rst_done,
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rx_pll_locked_m,
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rx_user_ready_m,
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rx_rst_done_m,
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// channel interface (tx)
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tx_p,
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tx_n,
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tx_out_clk,
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tx_clk,
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tx_rst,
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tx_rst_m,
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tx_data,
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tx_sysref,
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tx_sync,
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tx_pll_rst,
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tx_gt_rst,
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tx_gt_rst_m,
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tx_gt_charisk,
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tx_gt_data,
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tx_ip_rst,
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tx_ip_data,
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tx_ip_sysref,
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tx_ip_sync,
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tx_ip_rst_done,
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tx_pll_locked,
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tx_user_ready,
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tx_rst_done,
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tx_pll_locked_m,
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tx_user_ready_m,
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tx_rst_done_m,
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// dma interface
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up_es_dma_req,
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up_es_dma_addr,
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up_es_dma_data,
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up_es_dma_ack,
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up_es_dma_err,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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parameter integer ID = 0;
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parameter integer GTH_OR_GTX_N = 0;
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parameter [31:0] PMA_RSV = 32'h00018480;
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parameter integer CPLL_FBDIV = 2;
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parameter integer RX_OUT_DIV = 1;
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parameter integer RX_CLK25_DIV = 10;
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parameter integer RX_CLKBUF_ENABLE = 0;
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parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020;
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parameter integer TX_OUT_DIV = 1;
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parameter integer TX_CLK25_DIV = 10;
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parameter integer TX_CLKBUF_ENABLE = 0;
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// channel interface (pll)
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input cpll_rst_m;
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input cpll_ref_clk_in;
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input qpll_ref_clk;
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input qpll_locked;
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input qpll_clk;
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// channel interface (rx)
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input rx_p;
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input rx_n;
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output rx_out_clk;
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input rx_clk;
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output rx_rst;
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input rx_rst_m;
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output rx_sof;
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output [31:0] rx_data;
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input rx_sysref;
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output rx_sync;
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output rx_pll_rst;
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output rx_gt_rst;
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input rx_gt_rst_m;
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output [ 3:0] rx_gt_charisk;
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output [ 3:0] rx_gt_disperr;
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output [ 3:0] rx_gt_notintable;
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output [31:0] rx_gt_data;
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input rx_gt_comma_align_enb;
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output [ 3:0] rx_gt_ilas_f;
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output [ 3:0] rx_gt_ilas_q;
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output [ 3:0] rx_gt_ilas_a;
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output [ 3:0] rx_gt_ilas_r;
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output [ 3:0] rx_gt_cgs_k;
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output rx_ip_rst;
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input [ 3:0] rx_ip_sof;
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input [31:0] rx_ip_data;
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output rx_ip_sysref;
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input rx_ip_sync;
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output rx_ip_rst_done;
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output rx_pll_locked;
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output rx_user_ready;
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output rx_rst_done;
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input rx_pll_locked_m;
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input rx_user_ready_m;
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input rx_rst_done_m;
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// channel interface (tx)
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output tx_p;
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output tx_n;
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output tx_out_clk;
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input tx_clk;
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output tx_rst;
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input tx_rst_m;
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input [31:0] tx_data;
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input tx_sysref;
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input tx_sync;
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output tx_pll_rst;
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output tx_gt_rst;
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input tx_gt_rst_m;
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input [ 3:0] tx_gt_charisk;
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input [31:0] tx_gt_data;
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output tx_ip_rst;
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output [31:0] tx_ip_data;
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output tx_ip_sysref;
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output tx_ip_sync;
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output tx_ip_rst_done;
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output tx_pll_locked;
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output tx_user_ready;
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output tx_rst_done;
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input tx_pll_locked_m;
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input tx_user_ready_m;
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input tx_rst_done_m;
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// dma interface
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output up_es_dma_req;
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output [31:0] up_es_dma_addr;
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output [31:0] up_es_dma_data;
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input up_es_dma_ack;
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input up_es_dma_err;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal signals
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wire lpm_dfe_n_s;
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wire cpll_pd_s;
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wire [ 1:0] rx_sys_clk_sel_s;
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wire [ 2:0] rx_out_clk_sel_s;
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wire [ 1:0] tx_sys_clk_sel_s;
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wire [ 2:0] tx_out_clk_sel_s;
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wire up_drp_sel_s;
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wire up_drp_wr_s;
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wire [11:0] up_drp_addr_s;
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wire [15:0] up_drp_wdata_s;
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wire [15:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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wire [ 7:0] up_drp_rxrate_s;
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wire up_es_drp_sel_s;
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wire up_es_drp_wr_s;
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wire [11:0] up_es_drp_addr_s;
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wire [15:0] up_es_drp_wdata_s;
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wire [15:0] up_es_drp_rdata_s;
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wire up_es_drp_ready_s;
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wire up_es_start_s;
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wire up_es_stop_s;
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wire up_es_init_s;
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wire [ 4:0] up_es_prescale_s;
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wire [ 1:0] up_es_voffset_range_s;
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wire [ 7:0] up_es_voffset_step_s;
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wire [ 7:0] up_es_voffset_max_s;
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wire [ 7:0] up_es_voffset_min_s;
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wire [11:0] up_es_hoffset_max_s;
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wire [11:0] up_es_hoffset_min_s;
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wire [11:0] up_es_hoffset_step_s;
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wire [31:0] up_es_start_addr_s;
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wire [15:0] up_es_sdata0_s;
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wire [15:0] up_es_sdata1_s;
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wire [15:0] up_es_sdata2_s;
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wire [15:0] up_es_sdata3_s;
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wire [15:0] up_es_sdata4_s;
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wire [15:0] up_es_qdata0_s;
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wire [15:0] up_es_qdata1_s;
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wire [15:0] up_es_qdata2_s;
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wire [15:0] up_es_qdata3_s;
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wire [15:0] up_es_qdata4_s;
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wire up_es_status_s;
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// nothing to do for now
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assign tx_ip_data = tx_data;
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// instantiations
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ad_jesd_align i_align (
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.rx_clk (rx_clk),
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.rx_ip_sof (rx_ip_sof),
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.rx_ip_data (rx_ip_data),
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.rx_sof (rx_sof),
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.rx_data (rx_data));
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ad_gt_channel #(
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.GTH_OR_GTX_N (GTH_OR_GTX_N),
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.PMA_RSV (PMA_RSV),
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.CPLL_FBDIV (CPLL_FBDIV),
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.RX_OUT_DIV (RX_OUT_DIV),
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.TX_OUT_DIV (TX_OUT_DIV),
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.RX_CLK25_DIV (RX_CLK25_DIV),
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.TX_CLK25_DIV (TX_CLK25_DIV),
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.RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
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.TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
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.RX_CDR_CFG (RX_CDR_CFG))
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i_gt (
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.lpm_dfe_n (lpm_dfe_n_s),
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.cpll_ref_clk_in (cpll_ref_clk_in),
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.cpll_pd (cpll_pd_s),
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.cpll_rst (cpll_rst_m),
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.qpll_clk (qpll_clk),
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.qpll_ref_clk (qpll_ref_clk),
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.qpll_locked (qpll_locked),
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.rx_gt_rst_m (rx_gt_rst_m),
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.rx_p (rx_p),
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.rx_n (rx_n),
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.rx_sys_clk_sel (rx_sys_clk_sel_s),
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.rx_out_clk_sel (rx_out_clk_sel_s),
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.rx_out_clk (rx_out_clk),
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.rx_rst_done (rx_rst_done),
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.rx_pll_locked (rx_pll_locked),
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.rx_user_ready_m (rx_user_ready_m),
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.rx_clk (rx_clk),
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.rx_gt_charisk (rx_gt_charisk),
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.rx_gt_disperr (rx_gt_disperr),
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.rx_gt_notintable (rx_gt_notintable),
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.rx_gt_data (rx_gt_data),
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.rx_gt_comma_align_enb (rx_gt_comma_align_enb),
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.rx_gt_ilas_f (rx_gt_ilas_f),
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.rx_gt_ilas_q (rx_gt_ilas_q),
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.rx_gt_ilas_a (rx_gt_ilas_a),
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.rx_gt_ilas_r (rx_gt_ilas_r),
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.rx_gt_cgs_k (rx_gt_cgs_k),
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.tx_gt_rst_m (tx_gt_rst_m),
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.tx_p (tx_p),
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.tx_n (tx_n),
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.tx_sys_clk_sel (tx_sys_clk_sel_s),
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.tx_out_clk_sel (tx_out_clk_sel_s),
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.tx_out_clk (tx_out_clk),
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.tx_rst_done (tx_rst_done),
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.tx_pll_locked (tx_pll_locked),
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.tx_user_ready_m (tx_user_ready_m),
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.tx_clk (tx_clk),
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.tx_gt_charisk (tx_gt_charisk),
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.tx_gt_data (tx_gt_data),
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.up_clk (up_clk),
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.up_drp_sel (up_drp_sel_s),
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.up_drp_addr (up_drp_addr_s),
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.up_drp_wr (up_drp_wr_s),
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.up_drp_wdata (up_drp_wdata_s),
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.up_drp_rdata (up_drp_rdata_s),
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.up_drp_ready (up_drp_ready_s),
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.up_drp_rxrate (up_drp_rxrate_s));
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ad_gt_es #(
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.GTH_OR_GTX_N (GTH_OR_GTX_N))
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i_es (
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.lpm_dfe_n (lpm_dfe_n_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_es_drp_sel (up_es_drp_sel_s),
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.up_es_drp_wr (up_es_drp_wr_s),
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.up_es_drp_addr (up_es_drp_addr_s),
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.up_es_drp_wdata (up_es_drp_wdata_s),
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.up_es_drp_rdata (up_es_drp_rdata_s),
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.up_es_drp_ready (up_es_drp_ready_s),
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.up_es_dma_req (up_es_dma_req),
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.up_es_dma_addr (up_es_dma_addr),
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.up_es_dma_data (up_es_dma_data),
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.up_es_dma_ack (up_es_dma_ack),
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.up_es_start (up_es_start_s),
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.up_es_stop (up_es_stop_s),
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.up_es_init (up_es_init_s),
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.up_es_sdata0 (up_es_sdata0_s),
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.up_es_sdata1 (up_es_sdata1_s),
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.up_es_sdata2 (up_es_sdata2_s),
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.up_es_sdata3 (up_es_sdata3_s),
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.up_es_sdata4 (up_es_sdata4_s),
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.up_es_qdata0 (up_es_qdata0_s),
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.up_es_qdata1 (up_es_qdata1_s),
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.up_es_qdata2 (up_es_qdata2_s),
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.up_es_qdata3 (up_es_qdata3_s),
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.up_es_qdata4 (up_es_qdata4_s),
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.up_es_prescale (up_es_prescale_s),
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.up_es_hoffset_min (up_es_hoffset_min_s),
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.up_es_hoffset_max (up_es_hoffset_max_s),
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.up_es_hoffset_step (up_es_hoffset_step_s),
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.up_es_voffset_min (up_es_voffset_min_s),
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.up_es_voffset_max (up_es_voffset_max_s),
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.up_es_voffset_step (up_es_voffset_step_s),
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.up_es_voffset_range (up_es_voffset_range_s),
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.up_es_start_addr (up_es_start_addr_s),
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.up_es_status (up_es_status_s));
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up_gt_channel #(
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.ID (ID))
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i_up (
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.lpm_dfe_n (lpm_dfe_n_s),
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.cpll_pd (cpll_pd_s),
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.rx_pll_rst (rx_pll_rst),
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.rx_sys_clk_sel (rx_sys_clk_sel_s),
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.rx_out_clk_sel (rx_out_clk_sel_s),
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.rx_clk (rx_clk),
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.rx_gt_rst (rx_gt_rst),
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.rx_rst (rx_rst),
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.rx_rst_m (rx_rst_m),
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.rx_ip_rst (rx_ip_rst),
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.rx_sysref (rx_sysref),
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.rx_ip_sysref (rx_ip_sysref),
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.rx_ip_sync (rx_ip_sync),
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.rx_sync (rx_sync),
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.rx_rst_done (rx_rst_done),
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.rx_rst_done_m (rx_rst_done_m),
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.rx_pll_locked (rx_pll_locked),
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.rx_pll_locked_m (rx_pll_locked_m),
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.rx_user_ready (rx_user_ready),
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.rx_ip_rst_done (rx_ip_rst_done),
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.tx_pll_rst (tx_pll_rst),
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.tx_sys_clk_sel (tx_sys_clk_sel_s),
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.tx_out_clk_sel (tx_out_clk_sel_s),
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.tx_clk (tx_clk),
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.tx_gt_rst (tx_gt_rst),
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.tx_rst (tx_rst),
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.tx_rst_m (tx_rst_m),
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.tx_ip_rst (tx_ip_rst),
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.tx_sysref (tx_sysref),
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.tx_ip_sysref (tx_ip_sysref),
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.tx_sync (tx_sync),
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.tx_ip_sync (tx_ip_sync),
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.tx_rst_done (tx_rst_done),
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.tx_rst_done_m (tx_rst_done_m),
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.tx_pll_locked (tx_pll_locked),
|
|
.tx_pll_locked_m (tx_pll_locked_m),
|
|
.tx_user_ready (tx_user_ready),
|
|
.tx_ip_rst_done (tx_ip_rst_done),
|
|
.up_drp_sel (up_drp_sel_s),
|
|
.up_drp_wr (up_drp_wr_s),
|
|
.up_drp_addr (up_drp_addr_s),
|
|
.up_drp_wdata (up_drp_wdata_s),
|
|
.up_drp_rdata (up_drp_rdata_s),
|
|
.up_drp_ready (up_drp_ready_s),
|
|
.up_drp_rxrate (up_drp_rxrate_s),
|
|
.up_es_drp_sel (up_es_drp_sel_s),
|
|
.up_es_drp_wr (up_es_drp_wr_s),
|
|
.up_es_drp_addr (up_es_drp_addr_s),
|
|
.up_es_drp_wdata (up_es_drp_wdata_s),
|
|
.up_es_drp_rdata (up_es_drp_rdata_s),
|
|
.up_es_drp_ready (up_es_drp_ready_s),
|
|
.up_es_start (up_es_start_s),
|
|
.up_es_stop (up_es_stop_s),
|
|
.up_es_init (up_es_init_s),
|
|
.up_es_prescale (up_es_prescale_s),
|
|
.up_es_voffset_range (up_es_voffset_range_s),
|
|
.up_es_voffset_step (up_es_voffset_step_s),
|
|
.up_es_voffset_max (up_es_voffset_max_s),
|
|
.up_es_voffset_min (up_es_voffset_min_s),
|
|
.up_es_hoffset_max (up_es_hoffset_max_s),
|
|
.up_es_hoffset_min (up_es_hoffset_min_s),
|
|
.up_es_hoffset_step (up_es_hoffset_step_s),
|
|
.up_es_start_addr (up_es_start_addr_s),
|
|
.up_es_sdata0 (up_es_sdata0_s),
|
|
.up_es_sdata1 (up_es_sdata1_s),
|
|
.up_es_sdata2 (up_es_sdata2_s),
|
|
.up_es_sdata3 (up_es_sdata3_s),
|
|
.up_es_sdata4 (up_es_sdata4_s),
|
|
.up_es_qdata0 (up_es_qdata0_s),
|
|
.up_es_qdata1 (up_es_qdata1_s),
|
|
.up_es_qdata2 (up_es_qdata2_s),
|
|
.up_es_qdata3 (up_es_qdata3_s),
|
|
.up_es_qdata4 (up_es_qdata4_s),
|
|
.up_es_dma_err (up_es_dma_err),
|
|
.up_es_status (up_es_status_s),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq),
|
|
.up_waddr (up_waddr),
|
|
.up_wdata (up_wdata),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq),
|
|
.up_raddr (up_raddr),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
|