191 lines
5.8 KiB
Verilog
191 lines
5.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9152 #(
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parameter ID = 0,
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parameter DAC_DATAPATH_DISABLE = 0,
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parameter DEVICE_TYPE = 0) (
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// jesd interface
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// tx_clk is (line-rate/40)
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input tx_clk,
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output [127:0] tx_data,
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output tx_valid,
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input tx_ready,
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// dma interface
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output dac_clk,
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output dac_valid_0,
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output dac_enable_0,
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input [ 63:0] dac_ddata_0,
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output dac_valid_1,
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output dac_enable_1,
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input [ 63:0] dac_ddata_1,
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input dac_dovf,
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input dac_dunf,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 31:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [ 31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 31:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal clocks and resets
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wire dac_rst;
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wire up_clk;
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wire up_rstn;
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// internal signals
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wire [ 15:0] dac_data_0_0_s;
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wire [ 15:0] dac_data_0_1_s;
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wire [ 15:0] dac_data_0_2_s;
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wire [ 15:0] dac_data_0_3_s;
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wire [ 15:0] dac_data_1_0_s;
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wire [ 15:0] dac_data_1_1_s;
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wire [ 15:0] dac_data_1_2_s;
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wire [ 15:0] dac_data_1_3_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s;
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wire up_rack_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign tx_valid = 1'b1;
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// device interface
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axi_ad9152_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
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.tx_clk (tx_clk),
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.tx_data (tx_data),
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data_0_0 (dac_data_0_0_s),
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.dac_data_0_1 (dac_data_0_1_s),
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.dac_data_0_2 (dac_data_0_2_s),
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.dac_data_0_3 (dac_data_0_3_s),
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.dac_data_1_0 (dac_data_1_0_s),
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.dac_data_1_1 (dac_data_1_1_s),
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.dac_data_1_2 (dac_data_1_2_s),
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.dac_data_1_3 (dac_data_1_3_s));
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// core
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axi_ad9152_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data_0_0 (dac_data_0_0_s),
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.dac_data_0_1 (dac_data_0_1_s),
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.dac_data_0_2 (dac_data_0_2_s),
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.dac_data_0_3 (dac_data_0_3_s),
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.dac_data_1_0 (dac_data_1_0_s),
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.dac_data_1_1 (dac_data_1_1_s),
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.dac_data_1_2 (dac_data_1_2_s),
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.dac_data_1_3 (dac_data_1_3_s),
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.dac_valid_0 (dac_valid_0),
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.dac_enable_0 (dac_enable_0),
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.dac_ddata_0 (dac_ddata_0),
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.dac_valid_1 (dac_valid_1),
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.dac_enable_1 (dac_enable_1),
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.dac_ddata_1 (dac_ddata_1),
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.dac_dovf (dac_dovf),
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.dac_dunf (dac_dunf),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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