71 lines
2.0 KiB
Verilog
71 lines
2.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_dds_1 (
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// interface
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input clk,
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input [15:0] angle,
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input [15:0] scale,
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output reg [15:0] dds_data);
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// internal registers
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// internal signals
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wire [15:0] sine_s;
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wire [33:0] s1_data_s;
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// sine
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ad_dds_sine #(.DELAY_DATA_WIDTH(1)) i_dds_sine (
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.clk (clk),
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.angle (angle),
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.sine (sine_s),
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.ddata_in (1'b0),
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.ddata_out ());
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// scale
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ad_mul #(.DELAY_DATA_WIDTH(1)) i_dds_scale (
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.clk (clk),
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.data_a ({sine_s[15], sine_s}),
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.data_b ({scale[15], scale}),
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.data_p (s1_data_s),
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.ddata_in (1'b0),
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.ddata_out ());
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// dds data
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always @(posedge clk) begin
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dds_data <= s1_data_s[29:14];
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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