92 lines
2.7 KiB
Verilog
92 lines
2.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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module mdc_mdio #(
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parameter PHY_AD = 5'b10000) (
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input mdio_mdc,
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input mdio_in_w,
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input mdio_in_r,
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output reg [ 1:0] speed_select,
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output reg duplex_mode);
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localparam IDLE = 2'b01;
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localparam ACQUIRE = 2'b10;
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wire preamble;
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reg [ 1:0] current_state = IDLE;
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reg [ 1:0] next_state = IDLE;
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reg [31:0] data_in = 32'h0;
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reg [31:0] data_in_r = 32'h0;
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reg [ 5:0] data_counter = 6'h0;
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assign preamble = &data_in;
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always @(posedge mdio_mdc) begin
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current_state <= next_state;
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data_in <= {data_in[30:0], mdio_in_w};
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if (current_state == ACQUIRE) begin
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data_counter <= data_counter + 1;
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end else begin
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data_counter <= 0;
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end
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if (data_counter == 6'h1f) begin
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if (data_in[31] == 1'b0 && data_in[29:28]==2'b10 && data_in[27:23] == PHY_AD && data_in[22:18] == 5'h11) begin
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speed_select <= data_in_r[16:15] ;
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duplex_mode <= data_in_r[14];
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end
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end
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end
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always @(negedge mdio_mdc) begin
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data_in_r <= {data_in_r[30:0], mdio_in_r};
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end
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always @(*) begin
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case (current_state)
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IDLE: begin
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if (preamble == 1 && mdio_in_w == 0) begin
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next_state <= ACQUIRE;
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end else begin
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next_state <= IDLE;
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end
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end
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ACQUIRE: begin
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if (data_counter == 6'h1f) begin
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next_state <= IDLE;
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end else begin
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next_state <= ACQUIRE;
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end
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end
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default: begin
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next_state <= IDLE;
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end
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endcase
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end
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endmodule
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