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Laszlo Nagy 45dae0f3d3 ad9081_fmca_ebz/common: Connect sync at TPL level 
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
 		2022-02-07 19:14:01 +02:00
..
a10soc ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters 2021-11-12 13:04:57 +02:00
common ad9081_fmca_ebz/common: Connect sync at TPL level 2022-02-07 19:14:01 +02:00
vck190 ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
vcu118 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
vcu128 ad9081_fmca_ebz/vcu128: Remove ref clock replica 2021-11-22 16:18:29 +02:00
zc706 ad9081_fmca_ebz: Fix signal length parameter 2021-12-08 14:29:48 +02:00
zcu102 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Makefile Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Readme.md start adding some doc to the ./projects directory 2021-11-10 14:01:06 +02:00

Readme.md

AD9081-FMCA-EBZ HDL Project

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