pluto_hdl_adi/projects/ad9656_fmc/zcu102/system_top.v

148 lines
4.5 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
input ref_clk0_p,
input ref_clk0_n,
input ref_clk1_p,
input ref_clk1_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
output rx_sync_p,
output rx_sync_n,
input sysref_p,
input sysref_n,
output sysref_out_p,
output sysref_out_n,
output spi_csn_ad9508,
output spi_csn_ad9553,
output spi_csn_ad9656,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire [94:0] gpio_i;
wire [94:0] gpio_o;
wire [94:0] gpio_t;
wire [20:0] gpio_bd;
wire [ 2:0] spi_csn;
wire ref_clk0;
wire ref_clk1;
wire rx_sync;
wire sysref;
wire sysref_out;
assign gpio_bd_o = gpio_o[7:0];
assign gpio_i[94:21] = gpio_o[94:21];
assign gpio_i[20: 8] = gpio_bd_i;
assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
assign sysref_out = 0;
// instantiations
IBUFDS_GTE4 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (ref_clk0_p),
.IB (ref_clk0_n),
.O (ref_clk0),
.ODIV2 ());
IBUFDS_GTE4 i_ibufds_ref_clk1 (
.CEB (1'd0),
.I (ref_clk1_p),
.IB (ref_clk1_n),
.O (ref_clk1),
.ODIV2 ());
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_sysref_out (
.I (sysref_out),
.O (sysref_out_p),
.OB (sysref_out_n));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
assign spi_csn_ad9656 = spi_csn[0];
assign spi_csn_ad9508 = spi_csn[1];
assign spi_csn_ad9553 = spi_csn[2];
system_wrapper i_system_wrapper (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (ref_clk0),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (sysref),
.spi0_sclk (spi_clk),
.spi0_csn (spi_csn),
.spi0_miso (spi_miso),
.spi0_mosi (spi_mosi),
.spi1_sclk (),
.spi1_csn (),
.spi1_miso (1'b0),
.spi1_mosi ());
endmodule
// ***************************************************************************
// ***************************************************************************