ab10bd136e
There are boards (e.g. AD4630-24) which take the SCLK and echo back to the FPGA through a level shifter - doing this removes the effect of round-trip timing delays from the level shifter. This is commonly done whenever isolators are used since they are very slow. By setting the ECHO_SCLK parameter to 1, the IP will use the incoming echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still synchronous to the SPI clock, and it's generated after the last valid SDI latch. The designer's responsibility is to time the SDI shift registers in order to respect the design requirements. |
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| axi_spi_engine | ||
| interfaces | ||
| scripts | ||
| spi_engine_execution | ||
| spi_engine_interconnect | ||
| spi_engine_offload | ||