141 lines
4.5 KiB
Verilog
141 lines
4.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module adrv9001_tx #(
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parameter CMOS_LVDS_N = 0,
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parameter NUM_LANES = 4,
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parameter FPGA_TECHNOLOGY = 0,
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parameter USE_BUFG = 0,
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parameter USE_RX_CLK_FOR_TX = 0
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) (
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input ref_clk,
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input up_clk,
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input mssi_sync,
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input tx_output_enable,
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// physical interface (transmit)
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output tx_dclk_out_n_NC,
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output tx_dclk_out_p_dclk_out,
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input tx_dclk_in_n_NC,
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input tx_dclk_in_p_dclk_in,
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output tx_idata_out_n_idata0,
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output tx_idata_out_p_idata1,
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output tx_qdata_out_n_qdata2,
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output tx_qdata_out_p_qdata3,
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output tx_strobe_out_n_NC,
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output tx_strobe_out_p_strobe_out,
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input rx_clk_div,
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input rx_clk,
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input rx_ssi_rst,
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// internal resets and clocks
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output [31:0] dac_clk_ratio,
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input dac_rst,
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output dac_clk_div,
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input [7:0] dac_data_0,
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input [7:0] dac_data_1,
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input [7:0] dac_data_2,
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input [7:0] dac_data_3,
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input [7:0] dac_data_strb,
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input [7:0] dac_data_clk,
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input dac_data_valid
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);
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wire [6*8-1:0] serdes_in;
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wire [5:0] gpio_out;
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periphery_clk_buf tx_clk_buf(
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.inclk (tx_dclk_in_p_dclk_in),
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.outclk (tx_clk)
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);
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assign serdes_in = {dac_data_clk,
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dac_data_strb,
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dac_data_3,
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dac_data_2,
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dac_data_1,
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dac_data_0};
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assign {tx_dclk_out_p_dclk_out,
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tx_strobe_out_p_strobe_out,
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tx_qdata_out_p_qdata3,
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tx_qdata_out_n_qdata2,
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tx_idata_out_p_idata1,
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tx_idata_out_n_idata0} = gpio_out;
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genvar i;
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generate
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for (i = 0; i <= 5; i = i + 1) begin: g_ddr_o
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reg [7:0] shift_reg = 8'b0;
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wire [1:0] gpio_in;
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// DDR output
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adrv9001_gpio_out gpio_tx_out (
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.ck(tx_clk),
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.din(gpio_in),
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.pad_out(gpio_out[i])
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);
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always @(posedge tx_clk) begin
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if (dac_data_valid) begin
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shift_reg <= serdes_in[i*8+:8];
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end else begin
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shift_reg <= {shift_reg[5:0],2'b0};
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end
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end
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// Order of transmission:
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// gpio_in[0] - first
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// gpio_in[1] - last
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assign gpio_in = {shift_reg[6],shift_reg[7]};
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end
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endgenerate
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// No clock divider, qualifier used instead
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assign dac_clk_div = tx_clk;
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assign dac_clk = tx_clk;
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assign dac_clk_ratio = 1;
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endmodule
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