98 lines
3.5 KiB
Tcl
98 lines
3.5 KiB
Tcl
###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ip
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package require qsys 14.0
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package require quartus::device
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source ../../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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ad_ip_create axi_ltc235x {AXI LTC235x Interface} axi_ltc235x_elab
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set_module_property AUTHOR {Geronimo, John Erasmus Mari F.}
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set_module_property VALIDATION_CALLBACK info_param_validate
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ad_ip_files axi_ltc235x [list \
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$ad_hdl_dir/library/common/up_axi.v \
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$ad_hdl_dir/library/common/up_adc_common.v \
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$ad_hdl_dir/library/common/ad_rst.v \
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$ad_hdl_dir/library/common/up_xfer_cntrl.v \
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$ad_hdl_dir/library/common/up_xfer_status.v \
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$ad_hdl_dir/library/common/up_clock_mon.v \
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$ad_hdl_dir/library/common/up_adc_channel.v \
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$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
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axi_ltc235x_cmos.v \
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axi_ltc235x_lvds.v \
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axi_ltc235x.v]
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add_documentation_link "AXI_LTC235x IP core" https://wiki.analog.com/resources/fpga/docs/axi_ltc235x
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ad_ip_parameter ID INTEGER 0
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ad_ip_parameter XILINX_INTEL_N INTEGER 0
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ad_ip_parameter LVDS_CMOS_N INTEGER 0
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ad_ip_parameter LANE_0_ENABLE INTEGER 1
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ad_ip_parameter LANE_1_ENABLE INTEGER 1
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ad_ip_parameter LANE_2_ENABLE INTEGER 1
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ad_ip_parameter LANE_3_ENABLE INTEGER 1
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ad_ip_parameter LANE_4_ENABLE INTEGER 1
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ad_ip_parameter LANE_5_ENABLE INTEGER 1
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ad_ip_parameter LANE_6_ENABLE INTEGER 1
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ad_ip_parameter LANE_7_ENABLE INTEGER 1
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ad_ip_parameter EXTERNAL_CLK INTEGER 0
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ad_ip_parameter LTC235X_FAMILY INTEGER 0
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ad_ip_parameter NUM_CHANNELS INTEGER 8
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ad_ip_parameter DATA_WIDTH INTEGER 18
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adi_add_auto_fpga_spec_params
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proc axi_ltc235x_elab {} {
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# interfaces
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# physical interface
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add_interface device_if conduit end
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# common
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add_interface_port device_if busy busy Input 1
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add_interface_port device_if lvds_cmos_n lvds_cmos_n Output 1
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set interface [get_parameter_value LVDS_CMOS_N]
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switch $interface {
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"0" { ;# cmos
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add_interface_port device_if scki scki Output 1
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add_interface_port device_if scko scko Input 1
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add_interface_port device_if sdi sdi Output 1
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add_interface_port device_if sdo sdo Input 8}
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"1" { ;# lvds
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add_interface_port device_if scki_p scki_p Output 1
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add_interface_port device_if scki_n scki_n Output 1
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add_interface_port device_if scko_p scko_p Input 1
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add_interface_port device_if scko_n scko_n Input 1
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add_interface_port device_if sdi_p sdi_p Output 1
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add_interface_port device_if sdi_n sdi_n Output 1
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add_interface_port device_if sdo_p sdo_p Input 1
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add_interface_port device_if sdo_n sdo_n Input 1}
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}
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# clock
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ad_interface clock external_clk input 1
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# axi
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
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# others
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ad_interface signal adc_dovf Input 1 ovf
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set num_channels [get_parameter_value NUM_CHANNELS]
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for {set i 0} {$i < $num_channels} {incr i} {
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add_interface adc_ch_$i conduit end
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add_interface_port adc_ch_$i adc_enable_$i enable Output 1
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add_interface_port adc_ch_$i adc_valid_$i valid Output 1
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add_interface_port adc_ch_$i adc_data_$i data Output 32
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set_interface_property adc_ch_$i associatedClock if_external_clk
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set_interface_property adc_ch_$i associatedReset ""
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}
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}
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