80 lines
3.2 KiB
Verilog
80 lines
3.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module qpsk_demod (
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clk,
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data_qpsk_i,
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data_qpsk_q,
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data_valid,
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data_output
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);
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input clk;
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input [15:0] data_qpsk_i;
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input [15:0] data_qpsk_q;
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input data_valid;
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output [ 1:0] data_output;
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wire [15:0] filtered_data_i;
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wire [15:0] filtered_data_q;
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wire [ 7:0] demodulated_data;
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// output logic
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assign data_output = demodulated_data[1:0];
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// instantiation
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Raised_Cosine_Receive_Filter i_rx_filter (
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.clk(clk),
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.reset(1'b0),
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.enb_1_1_1(data_valid),
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.In1_re(data_qpsk_i),
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.In1_im(data_qpsk_q),
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.Out1_re(filtered_data_i),
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.Out1_im(filtered_data_q)
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);
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QPSK_Demodulator_Baseband i_qpsk_demod(
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.in0_re(filtered_data_i),
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.in0_im(filtered_data_q),
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.out0(demodulated_data)
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);
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endmodule
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