205 lines
6.7 KiB
Verilog
205 lines
6.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// allows conversions between the adc (or similar) interface to the dma (or similar).
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// * asymmetric bus widths in the range allowed by the fifo
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// * frequency -- dma can run slower at reduced channels
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// * drop or add channels -- post processing samples
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// * interface axis -- allows axi-stream interface
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//
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// in all cases bandwidth requirements must be met (read >= write).
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//
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// axis-interface support
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// * set DMA_READY_ENABLE parameter to 1.
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// * connect dma_wr as axis_valid, dma_wready as axis_ready
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// * make sure read bandwidth >= write bandwidth (or drop samples)
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// * some axis interface requires last (use a counter or such externally).
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//
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// the fifo is external- connect all the fifo_* signals to a fifo generator IP.
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// configure the IP to match the buswidths & clocks.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_wfifo (
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// adc interface
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adc_rst,
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adc_clk,
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adc_wr,
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adc_wdata,
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adc_wovf,
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// dma interface
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dma_clk,
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dma_wr,
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dma_wdata,
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dma_wready,
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dma_wovf,
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// fifo interface
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fifo_rst,
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fifo_rstn,
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fifo_wr,
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fifo_wdata,
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fifo_wovf,
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fifo_rd,
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fifo_rdata,
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fifo_rempty);
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// parameters
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parameter ADC_DATA_WIDTH = 32;
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parameter DMA_DATA_WIDTH = 64;
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parameter DMA_READY_ENABLE = 0;
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// adc interface
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input adc_rst;
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input adc_clk;
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input adc_wr;
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input [ADC_DATA_WIDTH-1:0] adc_wdata;
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output adc_wovf;
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// dma interface
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input dma_clk;
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output dma_wr;
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output [DMA_DATA_WIDTH-1:0] dma_wdata;
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input dma_wready;
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input dma_wovf;
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// fifo interface
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output fifo_rst;
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output fifo_rstn;
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output fifo_wr;
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output [ADC_DATA_WIDTH-1:0] fifo_wdata;
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input fifo_wovf;
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output fifo_rd;
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input [DMA_DATA_WIDTH-1:0] fifo_rdata;
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input fifo_rempty;
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// internal registers
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reg [ 1:0] adc_wovf_m = 'd0;
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reg adc_wovf = 'd0;
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reg dma_wr_int = 'd0;
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reg fifo_rst = 'd0;
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reg fifo_rst_p = 'd0;
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reg fifo_rstn = 'd0;
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// internal signals
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wire dma_wready_s;
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wire [DMA_DATA_WIDTH-1:0] dma_wdata_s;
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// adc overflow
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always @(posedge adc_clk) begin
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if (adc_rst == 1'b1) begin
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adc_wovf_m <= 2'd0;
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adc_wovf <= 1'b0;
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end else begin
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adc_wovf_m[0] <= dma_wovf | fifo_wovf;
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adc_wovf_m[1] <= adc_wovf_m[0];
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adc_wovf <= adc_wovf_m[1];
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end
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end
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// write
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assign fifo_wr = adc_wr;
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genvar m;
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generate
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for (m = 0; m < ADC_DATA_WIDTH; m = m + 1) begin: g_wdata
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assign fifo_wdata[m] = adc_wdata[(ADC_DATA_WIDTH-1)-m];
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end
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endgenerate
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// read
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assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
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assign fifo_rd = ~fifo_rempty & dma_wready_s;
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always @(posedge dma_clk) begin
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dma_wr_int <= fifo_rd;
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end
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genvar s;
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generate
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for (s = 0; s < DMA_DATA_WIDTH; s = s + 1) begin: g_rdata
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assign dma_wdata_s[s] = fifo_rdata[(DMA_DATA_WIDTH-1)-s];
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end
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endgenerate
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// reset & resetn
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always @(posedge dma_clk or posedge adc_rst) begin
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if (adc_rst == 1'b1) begin
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fifo_rst_p <= 1'd1;
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fifo_rst <= 1'd1;
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fifo_rstn <= 1'd0;
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end else begin
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fifo_rst_p <= 1'b0;
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fifo_rst <= fifo_rst_p;
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fifo_rstn <= ~fifo_rst_p;
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end
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end
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// axis
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ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
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.clk (dma_clk),
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.rst (fifo_rst),
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.valid (dma_wr_int),
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.last (1'd0),
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.data (dma_wdata_s),
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.inf_valid (dma_wr),
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.inf_last (),
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.inf_data (dma_wdata),
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.inf_ready (dma_wready_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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