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Lars-Peter Clausen abde4048e0 fmcomms1: Add extra AXI slice on ADC DMA path 
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2015-02-20 16:43:45 +01:00
library axi_dmac: Correctly handle shutdown for the request splitter 2015-02-19 17:22:23 +01:00
projects fmcomms1: Add extra AXI slice on ADC DMA path 2015-02-20 16:43:45 +01:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md README.md: General update 2015-01-29 12:46:19 +02:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

  • Vivado 2014.4
  • Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga