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Verilog 61.7%
Tcl 31.2%
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Adrian Costina ad5ef35b48 fmcomms1: modified *_bd.tcl files formatting 2014-03-26 12:05:42 +02:00
library axi_dmac: Delay up_ack by one clock cycle 2014-03-25 14:35:52 +01:00
projects fmcomms1: modified *_bd.tcl files formatting 2014-03-26 12:05:42 +02:00
.gitignore added gitignore 2014-03-05 10:47:16 -05:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Update README.md 2014-03-13 14:03:15 -04:00

README.md

hdl

Analog Devices HDL libraries and projects

http://wiki.analog.com/resources/fpga/docs/hdl/github

http://wiki.analog.com/resources/fpga/docs/hdl/regmap