Lars-Peter Clausen ca7a70650d axi_dmac: Delay up_ack by one clock cycle ... The read data also becomes available only with a delay of one clock cycle, sending the ack too early will result in bogus register reads. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2014-03-25 14:35:52 +01:00
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axi_ad9122	library/axi_ad9122,axi_ad9643: added	2014-03-11 12:13:25 -04:00
axi_ad9361	changed pcore version and made it local (top shouldn't override)	2014-03-14 12:02:16 -04:00
axi_ad9643	FMCOMMS1: Updated projects and axi_ad9643 core	2014-03-12 16:23:41 +02:00
axi_clkgen	pointers to directories	2014-02-28 16:58:30 -05:00
axi_dmac	axi_dmac: Delay up_ack by one clock cycle	2014-03-25 14:35:52 +01:00
axi_fifo	Added axi_dmac, axi_fifo and misc files in library	2014-03-06 18:16:02 +02:00
axi_hdmi_tx	pointers to directories	2014-02-28 16:58:30 -05:00
axi_i2s_adi	pointers to directories	2014-02-28 16:58:30 -05:00
axi_spdif_tx	pointers to directories	2014-02-28 16:58:30 -05:00
common	changed pcore version and made it local (top shouldn't override)	2014-03-14 12:02:16 -04:00
scripts	Fix default value of $ad_hdl_dir and $ad_phdl_dir	2014-03-12 18:18:47 +02:00
util_i2c_mixer	pointers to directories	2014-02-28 16:58:30 -05:00
util_rfifo	library/util_fifo: updates for read side	2014-03-10 14:48:14 -04:00
util_sync_reset	util_sync_reset: Fix polarity of the sync_resetn signal	2014-03-25 13:03:12 +01:00
util_wfifo	library/util_fifo: updates for read side	2014-03-10 14:48:14 -04:00