602 lines
23 KiB
Tcl
602 lines
23 KiB
Tcl
#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
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# chips from Analog Devices, incorporate them into your PCB level product, and
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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package require qsys
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_intel.tcl
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set version 19.1
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#
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# Wrapper module that instantiates and connects all the components required to
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# for a JESD204 link.
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#
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# The following components are created:
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# * Transceiver for each lane
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# * Transceiver lane PLL (TX only)
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# * Transceiver reset controller
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# * Link PLL
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# * JESD204 link layer processing
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# * JESD204 link layer processing control interface
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# * axi_adxcvr link management peripheral
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#
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ad_ip_create adi_jesd204 {Analog Devices JESD204}
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set_module_property VALIDATION_CALLBACK jesd204_validate
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set_module_property COMPOSITION_CALLBACK jesd204_compose
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING "" false {
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VISIBLE true
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}
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ad_ip_parameter DEVICE STRING "" false {
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SYSTEM_INFO DEVICE
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VISIBLE false
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}
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ad_ip_parameter TX_OR_RX_N BOOLEAN 0 false { \
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DISPLAY_HINT "radio" \
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DISPLAY_NAME "Data Path" \
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ALLOWED_RANGES { "0:Receive" "1:Transmit" }
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}
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ad_ip_parameter ID NATURAL 0 false { \
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DISPLAY_NAME "Core ID" \
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}
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ad_ip_parameter LANE_RATE FLOAT 10000 false { \
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DISPLAY_NAME "Lane Rate" \
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DISPLAY_UNITS "Mbps" \
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}
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ad_ip_parameter SYSCLK_FREQUENCY FLOAT 100.0 false { \
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DISPLAY_NAME "System Clock Frequency" \
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UNITS Megahertz
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}
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ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false { \
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DISPLAY_NAME "Reference Clock Frequency" \
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UNITS Megahertz \
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}
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ad_ip_parameter NUM_OF_LANES POSITIVE 4 false { \
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DISPLAY_NAME "Number of Lanes" \
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ALLOWED_RANGES 1:8
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}
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ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN 0 false { \
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DISPLAY_HINT "Clock Network" \
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DISPLAY_NAME "Clock Network" \
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ALLOWED_RANGES { "0:x1/xN (Non-bonded)" "1:x6/xN (Bonded)" }
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}
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ad_ip_parameter LANE_MAP STRING "" false { \
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DISPLAY_NAME "Lane Mapping" \
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}
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ad_ip_parameter LANE_INVERT STD_LOGIC_VECTOR 0 false { \
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DISPLAY_NAME "Lane Invert Mask" \
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DISPLAY_HINT "hexadecimal" \
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WIDTH 8 \
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}
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ad_ip_parameter SOFT_PCS BOOLEAN true false { \
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DISPLAY_NAME "Enable Soft PCS" \
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}
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ad_ip_parameter INPUT_PIPELINE_STAGES INTEGER 0 false { \
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DISPLAY_NAME "Enable input pipeline" \
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}
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ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN 0 false { \
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DISPLAY_NAME "External Device Clock Enable" \
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}
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proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
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global version
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set device [get_parameter_value DEVICE_FAMILY]
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if {[string equal $device "Arria 10"]} {
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add_instance phy_reset_control altera_xcvr_reset_control $version
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set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true
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set_instance_parameter_value phy_reset_control {SYNCHRONIZE_RESET} {0}
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set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
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set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
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set_instance_parameter_value phy_reset_control {TX_PLL_ENABLE} $tx
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set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx
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set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx]
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add_connection sys_clock.clk phy_reset_control.clock
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add_connection link_reset.out_reset phy_reset_control.reset
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add_connection sys_clock.clk_reset phy_reset_control.reset
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if {$tx} {
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set_instance_parameter_value phy_reset_control {T_PLL_POWERDOWN} {1000}
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set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1}
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set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {70000}
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set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {70000}
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add_connection phy_reset_control.tx_ready axi_xcvr.ready
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} else {
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set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {70000}
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set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {4000}
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add_connection phy_reset_control.rx_ready axi_xcvr.ready
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}
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} elseif {[string equal $device "Stratix 10"]} {
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add_instance phy_reset_control altera_xcvr_reset_control_s10 $version
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set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
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set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
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set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx
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set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx]
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set_instance_parameter_value phy_reset_control {REDUCED_SIM_TIME} {1}
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set_instance_parameter_value phy_reset_control {T_PLL_POWERDOWN} {1000}
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set_instance_parameter_value phy_reset_control {T_PLL_LOCK_HYST} {1000}
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add_connection sys_clock.clk phy_reset_control.clock
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add_connection link_reset.out_reset phy_reset_control.reset
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add_connection sys_clock.clk_reset phy_reset_control.reset
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if {$tx} {
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set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1}
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set_instance_parameter_value phy_reset_control {TX_MANUAL_RESET} {0}
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set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {0}
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set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {20}
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add_connection phy_reset_control.tx_ready axi_xcvr.ready
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} else {
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set_instance_parameter_value phy_reset_control {RX_MANUAL_RESET} {0}
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set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {40}
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set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {5000}
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add_connection phy_reset_control.rx_ready axi_xcvr.ready
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}
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} else {
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send_message error "Only Arria 10 and Stratix 10 are supported."
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}
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}
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proc create_lane_pll {id tx_or_rx_n pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} {
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global version
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set device_family [get_parameter_value "DEVICE_FAMILY"]
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if {$device_family == "Arria 10"} {
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add_instance lane_pll altera_xcvr_atx_pll_a10 $version
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if {$num_lanes > 6} {
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set_instance_parameter_value lane_pll enable_mcgb {true}
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if {$bonding_clocks_en} {
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set_instance_parameter_value lane_pll {enable_bonding_clks} {true}
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set_instance_parameter_value lane_pll {mcgb_div} {1}
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set_instance_parameter_value lane_pll {set_ref_clk_div} {1}
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set_instance_parameter_value lane_pll {pma_width} {40}
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} else {
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set_instance_parameter_value lane_pll enable_hfreq_clk {true}
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}
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add_instance glue adi_jesd204_glue 1.0
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add_connection phy_reset_control.pll_powerdown glue.in_pll_powerdown
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add_connection glue.out_pll_powerdown lane_pll.pll_powerdown
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add_connection glue.out_mcgb_rst lane_pll.mcgb_rst
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} else {
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add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown
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}
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set_instance_parameter_value lane_pll {enable_pll_reconfig} {1}
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} elseif {$device_family == "Stratix 10"} {
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add_instance lane_pll altera_xcvr_atx_pll_s10_htile $version
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set_instance_parameter_value lane_pll {rcfg_enable} {1}
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## tie pll_select to GND
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add_instance glue adi_jesd204_glue 1.0
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set_instance_parameter_value glue {IN_PLL_POWERDOWN_EN} {0}
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if {$tx_or_rx_n} {
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add_connection glue.out_pll_select_gnd phy_reset_control.pll_select
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}
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} else {
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send_message error "Only Arria 10 and Stratix 10 are supported."
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}
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set_instance_parameter_value lane_pll {rcfg_separate_avmm_busy} {1}
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set_instance_parameter_value lane_pll {set_capability_reg_enable} {1}
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set_instance_parameter_value lane_pll {set_user_identifier} $id
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set_instance_parameter_value lane_pll {set_csr_soft_logic_enable} {1}
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set_instance_parameter_value lane_pll {set_output_clock_frequency} $pllclk_frequency
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set_instance_parameter_value lane_pll {set_auto_reference_clock_frequency} $refclk_frequency
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add_connection lane_pll.pll_locked phy_reset_control.pll_locked
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add_connection lane_pll.pll_cal_busy phy_reset_control.pll_cal_busy
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add_connection ref_clock.out_clk lane_pll.pll_refclk0
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add_connection sys_clock.clk lane_pll.reconfig_clk0
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add_connection sys_clock.clk_reset lane_pll.reconfig_reset0
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add_interface lane_pll_reconfig avalon slave
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set_interface_property lane_pll_reconfig EXPORT_OF lane_pll.reconfig_avmm0
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}
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proc jesd204_get_max_lane_rate {device soft_pcs} {
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if {[string range $device 0 2] == "10A"} {
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set device_speedgrade [string range $device 13 13]
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set pma_speedgrade [string range $device 8 8]
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} elseif {[string range $device 0 1] == "1S"} {
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set device_speedgrade [string range $device 13 13]
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set pma_speedgrade [string range $device 8 8]
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} else {
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# Assume fastest speed grade
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set device_speedgrade 1
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set pma_speedgrade 1
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}
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if {$soft_pcs} {
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if {$pma_speedgrade == 1 || $pma_speedgrade == 2} {
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return "15000"
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} elseif {$pma_speedgrade == 3} {
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return "14200"
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} else {
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return "12500"
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}
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} else {
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if {$device_speedgrade == 1} {
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return "12000"
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} elseif {$device_speedgrade == 2} {
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return "9830"
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} else {
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return "8936"
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}
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}
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}
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proc jesd204_validate {{quiet false}} {
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set soft_pcs [get_parameter_value "SOFT_PCS"]
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set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"]
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set device_family [get_parameter_value "DEVICE_FAMILY"]
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set device [get_parameter_value "DEVICE"]
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set lane_rate [get_parameter_value "LANE_RATE"]
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set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
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set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
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if {$device_family != "Arria 10" && $device_family != "Stratix 10"} {
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if {!$quiet} {
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send_message error "Only Arria 10 and Startix 10 are supported."
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}
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return false
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}
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set max_lane_rate [jesd204_get_max_lane_rate $device $soft_pcs]
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if {$lane_rate < 2000 || $lane_rate > $max_lane_rate} {
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if {!$quiet} {
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send_message error "Lane rate must be in the range 2000-${max_lane_rate} Mbps."
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if {!$soft_pcs} {
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send_message error "Consider enabling soft PCS for a higher maximum lane rate."
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if {$input_pipeline} {
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send_message error "Input pipeline can be active just when soft PCS is used."
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}
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}
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}
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return false
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}
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set_parameter_property BONDING_CLOCKS_EN VISIBLE [expr ($num_of_lanes > 6) && ($tx_or_rx_n)]
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return true
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}
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proc jesd204_compose {} {
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global version
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set id [get_parameter_value "ID"]
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set lane_rate [get_parameter_value "LANE_RATE"]
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set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
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set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
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set sysclk_frequency [get_parameter_value "SYSCLK_FREQUENCY"]
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set refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
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set lane_map [get_parameter_value "LANE_MAP"]
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set lane_invert [get_parameter_value "LANE_INVERT"]
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set soft_pcs [get_parameter_value "SOFT_PCS"]
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set device_family [get_parameter_value "DEVICE_FAMILY"]
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set device [get_parameter_value "DEVICE"]
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set ext_device_clk_en [get_parameter_value "EXT_DEVICE_CLK_EN"]
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set bonding_clocks_en [get_parameter_value "BONDING_CLOCKS_EN"]
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set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"]
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set pllclk_frequency [expr $lane_rate / 2]
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set linkclk_frequency [expr $lane_rate / 40]
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if {![jesd204_validate true]} {
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return
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}
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add_instance sys_clock clock_source 19.2
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set_instance_parameter_value sys_clock {clockFrequency} [expr $sysclk_frequency*1000000]
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set_instance_parameter_value sys_clock {resetSynchronousEdges} {deassert}
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add_interface sys_clk clock sink
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set_interface_property sys_clk EXPORT_OF sys_clock.clk_in
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add_interface sys_resetn reset sink
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set_interface_property sys_resetn EXPORT_OF sys_clock.clk_in_reset
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add_instance ref_clock altera_clock_bridge $version
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set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000]
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF ref_clock.in_clk
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set outclk_name ""
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## link clock configuration (also known as device clock, which will be used
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## by the upper layers for the data path, it can come from the PCS or external)
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add_instance link_clock altera_clock_bridge $version
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set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
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set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2
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add_instance link_reset altera_reset_bridge $version
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set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2
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if {$device_family == "Arria 10"} {
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add_instance link_pll altera_xcvr_fpll_a10 $version
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set_instance_parameter_value link_pll {gui_fpll_mode} {0}
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set_instance_parameter_value link_pll {gui_reference_clock_frequency} $refclk_frequency
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set_instance_parameter_value link_pll {gui_number_of_output_clocks} 1
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set_instance_parameter_value link_pll {gui_desired_outclk0_frequency} $linkclk_frequency
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set_instance_parameter_value link_pll {enable_pll_reconfig} {1}
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set outclk_name "outclk0"
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add_instance link_pll_reset_control altera_xcvr_reset_control $version
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set_instance_parameter_value link_pll_reset_control {SYNCHRONIZE_RESET} {0}
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set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
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set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1}
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set_instance_parameter_value link_pll_reset_control {T_PLL_POWERDOWN} {1000}
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set_instance_parameter_value link_pll_reset_control {TX_ENABLE} {0}
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set_instance_parameter_value link_pll_reset_control {RX_ENABLE} {0}
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add_connection sys_clock.clk link_pll_reset_control.clock
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add_connection link_reset.out_reset link_pll_reset_control.reset
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add_connection sys_clock.clk_reset link_pll_reset_control.reset
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add_connection link_pll_reset_control.pll_powerdown link_pll.pll_powerdown
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} elseif {$device_family == "Stratix 10"} {
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send_message info "Instantiate a fpll_s10_htile for link_pll."
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add_instance link_pll altera_xcvr_fpll_s10_htile 19.1.1
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## Primary Use is Core mode
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set_instance_parameter_value link_pll {set_primary_use} 0
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## Basic Mode
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set_instance_parameter_value link_pll {set_prot_mode} 0
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set_instance_parameter_value link_pll {message_level} {error}
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set_instance_parameter_value link_pll {set_refclk_cnt} {1}
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set_instance_parameter_value link_pll {set_auto_reference_clock_frequency} $refclk_frequency
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set_instance_parameter_value link_pll {set_output_clock_frequency} $linkclk_frequency
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set_instance_parameter_value link_pll {set_bw_sel} {medium}
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set_instance_parameter_value link_pll {rcfg_enable} {1}
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set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1}
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set_instance_parameter_value link_pll {set_capability_reg_enable} {1}
|
|
|
|
set outclk_name "outclk_div1"
|
|
|
|
} else {
|
|
## Unsupported device
|
|
send_message error "Only Arria 10 and Stratix 10 are supported."
|
|
}
|
|
|
|
add_connection link_pll.$outclk_name link_clock.in_clk
|
|
add_interface link_clk clock source
|
|
|
|
add_connection sys_clock.clk link_reset.clk
|
|
add_interface link_reset reset source
|
|
set_interface_property link_reset EXPORT_OF link_reset.out_reset_1
|
|
|
|
set_instance_parameter_value link_pll {set_capability_reg_enable} {1}
|
|
set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1}
|
|
set_instance_parameter_value link_pll {rcfg_separate_avmm_busy} {1}
|
|
add_connection ref_clock.out_clk link_pll.pll_refclk0
|
|
|
|
add_connection sys_clock.clk_reset link_pll.reconfig_reset0
|
|
add_connection sys_clock.clk link_pll.reconfig_clk0
|
|
|
|
add_instance axi_xcvr axi_adxcvr 1.0
|
|
set_instance_parameter_value axi_xcvr {ID} $id
|
|
set_instance_parameter_value axi_xcvr {TX_OR_RX_N} $tx_or_rx_n
|
|
set_instance_parameter_value axi_xcvr {NUM_OF_LANES} $num_of_lanes
|
|
|
|
add_connection sys_clock.clk axi_xcvr.s_axi_clock
|
|
add_connection sys_clock.clk_reset axi_xcvr.s_axi_reset
|
|
add_connection axi_xcvr.if_up_rst link_reset.in_reset
|
|
add_connection link_pll.pll_locked axi_xcvr.core_pll_locked
|
|
|
|
add_interface link_management axi4lite slave
|
|
set_interface_property link_management EXPORT_OF axi_xcvr.s_axi
|
|
|
|
add_interface link_pll_reconfig avalon slave
|
|
set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0
|
|
set_interface_property link_pll_reconfig associatedClock sys_clk
|
|
set_interface_property link_pll_reconfig associatedReset sys_resetn
|
|
|
|
|
|
create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency
|
|
|
|
add_instance phy jesd204_phy 1.0
|
|
set_instance_parameter_value phy ID $id
|
|
set_instance_parameter_value phy DEVICE $device_family
|
|
set_instance_parameter_value phy SOFT_PCS $soft_pcs
|
|
set_instance_parameter_value phy TX_OR_RX_N $tx_or_rx_n
|
|
set_instance_parameter_value phy LANE_RATE $lane_rate
|
|
set_instance_parameter_value phy REFCLK_FREQUENCY $refclk_frequency
|
|
set_instance_parameter_value phy NUM_OF_LANES $num_of_lanes
|
|
set_instance_parameter_value phy REGISTER_INPUTS $input_pipeline
|
|
set_instance_parameter_value phy LANE_INVERT $lane_invert
|
|
set_instance_parameter_value phy EXT_DEVICE_CLK_EN $ext_device_clk_en
|
|
set_instance_parameter_value phy BONDING_CLOCKS_EN $bonding_clocks_en
|
|
|
|
add_connection link_clock.out_clk_1 phy.link_clk
|
|
add_connection link_reset.out_reset phy.link_reset
|
|
add_connection sys_clock.clk phy.reconfig_clk
|
|
add_connection sys_clock.clk_reset phy.reconfig_reset
|
|
|
|
## connect the required device clock
|
|
|
|
if {$ext_device_clk_en} {
|
|
add_instance ext_device_clock altera_clock_bridge $version
|
|
set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
|
|
set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2
|
|
add_interface device_clk clock sink
|
|
set_interface_property device_clk EXPORT_OF ext_device_clock.in_clk
|
|
add_connection ext_device_clock.out_clk phy.device_clk
|
|
set_interface_property link_clk EXPORT_OF ext_device_clock.out_clk_1
|
|
} else {
|
|
set_interface_property link_clk EXPORT_OF link_clock.out_clk
|
|
}
|
|
|
|
set phy_reset_intfs_s10 {analogreset_stat digitalreset_stat}
|
|
|
|
if {$tx_or_rx_n} {
|
|
set tx_rx "tx"
|
|
set data_direction sink
|
|
set jesd204_intfs {config control ilas_config event status}
|
|
set phy_reset_intfs {analogreset digitalreset cal_busy}
|
|
|
|
create_lane_pll $id $tx_or_rx_n $pllclk_frequency $refclk_frequency $num_of_lanes $bonding_clocks_en
|
|
if {$num_of_lanes > 6} {
|
|
if {$bonding_clocks_en} {
|
|
add_connection lane_pll.tx_bonding_clocks phy.bonding_clocks
|
|
} else {
|
|
add_connection lane_pll.tx_serial_clk phy.serial_clk_x1
|
|
add_connection lane_pll.mcgb_serial_clk phy.serial_clk_xN
|
|
}
|
|
} else {
|
|
add_connection lane_pll.tx_serial_clk phy.serial_clk_x1
|
|
}
|
|
} else {
|
|
set tx_rx "rx"
|
|
set data_direction source
|
|
set jesd204_intfs {config ilas_config event status}
|
|
set phy_reset_intfs {analogreset digitalreset cal_busy is_lockedtodata}
|
|
|
|
add_connection ref_clock.out_clk phy.ref_clk
|
|
}
|
|
|
|
add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} 1.0
|
|
set_instance_parameter_value axi_jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
|
|
|
|
add_connection sys_clock.clk axi_jesd204_${tx_rx}.s_axi_clock
|
|
add_connection sys_clock.clk_reset axi_jesd204_${tx_rx}.s_axi_reset
|
|
|
|
add_instance jesd204_${tx_rx} jesd204_${tx_rx} 1.0
|
|
set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
|
|
|
|
if {$ext_device_clk_en} {
|
|
add_connection ext_device_clock.out_clk axi_jesd204_${tx_rx}.core_clock
|
|
add_connection ext_device_clock.out_clk jesd204_${tx_rx}.clock
|
|
} else {
|
|
add_connection link_clock.out_clk_1 axi_jesd204_${tx_rx}.core_clock
|
|
add_connection link_clock.out_clk_1 jesd204_${tx_rx}.clock
|
|
}
|
|
|
|
add_connection link_reset.out_reset axi_jesd204_${tx_rx}.core_reset_ext
|
|
add_connection axi_jesd204_${tx_rx}.core_reset jesd204_${tx_rx}.reset
|
|
|
|
foreach intf $jesd204_intfs {
|
|
add_connection axi_jesd204_${tx_rx}.${intf} jesd204_${tx_rx}.${intf}
|
|
}
|
|
|
|
foreach intf $phy_reset_intfs {
|
|
add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf}
|
|
}
|
|
|
|
## connect phy_reset_control interfaces specific to Stratix 10
|
|
if {$device_family == "Stratix 10"} {
|
|
foreach intf $phy_reset_intfs_s10 {
|
|
add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf}
|
|
}
|
|
|
|
}
|
|
|
|
set lane_map [regexp -all -inline {\S+} $lane_map]
|
|
for {set i 0} {$i < $num_of_lanes} {incr i} {
|
|
if {$lane_map != {}} {
|
|
set j [lindex $lane_map $i]
|
|
} else {
|
|
set j $i
|
|
}
|
|
|
|
add_connection jesd204_${tx_rx}.${tx_rx}_phy${j} phy.phy_${i}
|
|
}
|
|
|
|
for {set i 0} {$i < $num_of_lanes} {incr i} {
|
|
add_interface phy_reconfig_${i} avalon slave
|
|
set_interface_property phy_reconfig_${i} EXPORT_OF phy.reconfig_avmm_${i}
|
|
}
|
|
|
|
add_interface interrupt interrupt end
|
|
set_interface_property interrupt EXPORT_OF axi_jesd204_${tx_rx}.interrupt
|
|
add_interface link_reconfig axi4lite slave
|
|
set_interface_property link_reconfig EXPORT_OF axi_jesd204_${tx_rx}.s_axi
|
|
|
|
add_interface link_data avalon_streaming $data_direction
|
|
set_interface_property link_data EXPORT_OF jesd204_${tx_rx}.${tx_rx}_data
|
|
|
|
if {!$tx_or_rx_n} {
|
|
add_interface link_sof conduit end
|
|
set_interface_property link_sof EXPORT_OF jesd204_rx.rx_sof
|
|
}
|
|
|
|
add_interface sysref conduit end
|
|
set_interface_property sysref EXPORT_OF jesd204_${tx_rx}.sysref
|
|
|
|
add_interface sync conduit end
|
|
set_interface_property sync EXPORT_OF jesd204_${tx_rx}.sync
|
|
|
|
add_interface serial_data conduit end
|
|
set_interface_property serial_data EXPORT_OF phy.serial_data
|
|
|
|
}
|