Istvan Csomortani ad8d2d225f de10: Delete redundant base design		2020-09-15 18:14:23 +03:00
..
a10gx	sysid_intel: Added sysid to intel projects	2020-09-11 15:46:06 +03:00
a10soc	sysid_intel: Added sysid to intel projects	2020-09-11 15:46:06 +03:00
ac701	system_id: deployed ip	2019-08-06 16:53:11 +03:00
c5soc	sysid_intel: Added sysid to intel projects	2020-09-11 15:46:06 +03:00
coraz7s	cn0540: Initial commit	2020-05-28 18:49:35 +03:00
de10nano	common/de10nano: Add de10nano base design	2020-09-15 18:14:23 +03:00
intel	avl_dacfifo: add_intance command must have a version attribute	2020-08-11 10:14:18 +03:00
kc705	…
kcu105	system_id: deployed ip	2019-08-06 16:53:11 +03:00
microzed	…
s10soc	s10soc: Insert an additional bridge between DMA and HPS	2020-09-09 14:15:37 +03:00
vc707	system_id: deployed ip	2019-08-06 16:53:11 +03:00
vcu118	…
xilinx	adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock	2019-12-03 17:27:56 +02:00
zc702	zynq:all: fix SPI clock constraint	2019-08-09 16:39:56 +03:00
zc706	zynq:all: fix SPI clock constraint	2019-08-09 16:39:56 +03:00
zcu102	zynq:all: fix SPI clock constraint	2019-08-09 16:39:56 +03:00
zed	…