cycollineau b93c1e6e90 intel/adi_jesd204: add bonded clock network support (#408) ... * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>		2020-01-09 17:45:32 +02:00
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adi_jesd204	intel/adi_jesd204: add bonded clock network support (#408)	2020-01-09 17:45:32 +02:00
avl_adxcfg	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
avl_adxcvr	avl_adxcvr: Rename variables with alt_* pre-fix	2019-06-29 06:53:51 +03:00
avl_adxcvr_octet_swap	library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl	2019-06-29 06:53:51 +03:00
avl_adxphy	library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl	2019-06-29 06:53:51 +03:00
avl_dacfifo	scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface	2019-06-29 06:53:51 +03:00
axi_adxcvr	intel/axi_adxcvr_up: Add device spec register	2019-10-02 08:39:01 +03:00
common	intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym	2019-06-29 06:53:51 +03:00
jesd204_phy	intel/adi_jesd204: add bonded clock network support (#408)	2020-01-09 17:45:32 +02:00
util_clkdiv	scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface	2019-06-29 06:53:51 +03:00