337 lines
10 KiB
Verilog
337 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_dacfifo #(
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parameter ADDRESS_WIDTH = 6,
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parameter DATA_WIDTH = 128) (
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// DMA interface
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input dma_clk,
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input dma_rst,
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input dma_valid,
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input [(DATA_WIDTH-1):0] dma_data,
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output reg dma_ready,
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input dma_xfer_req,
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input dma_xfer_last,
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// DAC interface
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input dac_clk,
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input dac_rst,
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input dac_valid,
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output reg [(DATA_WIDTH-1):0] dac_data,
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output reg dac_dunf,
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output reg dac_xfer_out,
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input bypass);
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localparam FIFO_THRESHOLD_HI = {(ADDRESS_WIDTH){1'b1}} - 4;
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// internal registers
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reg dma_init = 1'b0;
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reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dma_waddr_g = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_g = 'b0;
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reg dma_bypass = 1'b0;
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reg dma_bypass_m1 = 1'b0;
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reg dma_xfer_req_d1 = 1'b0;
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reg dma_xfer_req_d2 = 1'b0;
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reg dma_xfer_out_fifo = 1'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_waddr = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_waddr_m1 = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_waddr_m2 = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_addr_diff = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m1 = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m2 = 'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_lastaddr = 'b0;
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reg dac_mem_ready = 1'b0;
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reg dac_xfer_req_m1 = 1'b0;
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reg dac_xfer_req = 1'b0;
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reg dac_xfer_req_d = 1'b0;
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reg dac_xfer_out_fifo = 1'b0;
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reg dac_xfer_out_fifo_m1 = 1'b0;
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reg dac_xfer_out_fifo_d = 1'b0;
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reg dac_bypass = 1'b0;
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reg dac_bypass_m1 = 1'b0;
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// internal wires
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wire dma_rst_int_s;
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wire dma_wren_s;
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wire dma_xfer_posedge_s;
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wire dma_ready_bypass_s;
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wire [(DATA_WIDTH-1):0] dac_data_fifo_s;
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wire [(DATA_WIDTH-1):0] dac_data_bypass_s;
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wire [ADDRESS_WIDTH:0] dac_addr_diff_s;
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wire [(ADDRESS_WIDTH-1):0] dma_waddr_b2g_s;
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wire [(ADDRESS_WIDTH-1):0] dac_waddr_g2b_s;
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wire [(ADDRESS_WIDTH-1):0] dac_lastaddr_g2b_s;
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wire dac_mem_ren_s;
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wire dac_xfer_posedge_s;
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wire dac_rst_int_s;
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// internal reset generation
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always @(posedge dma_clk) begin
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dma_xfer_req_d1 <= dma_xfer_req;
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dma_xfer_req_d2 <= dma_xfer_req_d1;
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end
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assign dma_xfer_posedge_s = ~dma_xfer_req_d2 & dma_xfer_req_d1;
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// status register indicating that the module is in initialization phase
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always @(posedge dma_clk) begin
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if ((dma_rst == 1'b1) || (dma_xfer_last == 1'b1)) begin
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dma_init <= 1'b0;
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end else begin
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if (dma_xfer_posedge_s == 1'b1) begin
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dma_init <= 1'b1;
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end
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end
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end
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// if the module is not in initialization phase, it should go
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// into reset at a positive edge of dma_xfer_req
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assign dma_rst_int_s = dma_rst | (dma_xfer_posedge_s & ~dma_init);
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// DMA / Write interface
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// write address generation
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assign dma_wren_s = dma_valid & dma_ready;
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always @(posedge dma_clk) begin
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if(dma_rst_int_s == 1'b1) begin
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dma_waddr <= 'b0;
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dma_waddr_g <= 'b0;
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dma_xfer_out_fifo <= 1'b0;
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end else begin
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if (dma_wren_s == 1'b1) begin
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dma_waddr <= dma_waddr + 1'b1;
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end
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if (dma_xfer_last == 1'b1) begin
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dma_waddr <= 'b0;
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dma_xfer_out_fifo <= 1'b1;
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end
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dma_waddr_g <= dma_waddr_b2g_s;
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end
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end
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ad_b2g #(
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.DATA_WIDTH (ADDRESS_WIDTH))
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i_dma_waddr_b2g (
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.din (dma_waddr),
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.dout (dma_waddr_b2g_s));
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// save the last write address
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always @(posedge dma_clk) begin
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if (dma_rst_int_s == 1'b1) begin
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dma_lastaddr_g <= 'b0;
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end else begin
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if (dma_bypass == 1'b0) begin
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dma_lastaddr_g <= (dma_xfer_last == 1'b1)? dma_waddr_b2g_s : dma_lastaddr_g;
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end
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end
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end
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// DAC / Read interface
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always @(posedge dac_clk) begin
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dac_xfer_req_m1 <= dma_xfer_req;
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dac_xfer_req <= dac_xfer_req_m1;
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dac_xfer_req_d <= dac_xfer_req;
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end
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assign dac_xfer_posedge_s = ~dac_xfer_req_d & dac_xfer_req;
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// we can reset the DAC side at each positive edge of xfer_req, even if
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// sometimes the reset is redundant
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assign dac_rst_int_s = dac_xfer_req | dac_rst;
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assign dac_addr_diff_s = {1'b1, dac_waddr} - dac_raddr;
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// The memory module is ready if it's not empty
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always @(posedge dac_clk) begin
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if (dac_rst_int_s == 1'b1) begin
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dac_addr_diff <= 'b0;
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dac_waddr_m1 <= 'b0;
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dac_waddr_m2 <= 'b0;
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dac_waddr <= 'b0;
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dac_mem_ready <= 1'b0;
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end else begin
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dac_waddr_m1 <= dma_waddr_g;
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dac_waddr_m2 <= dac_waddr_m1;
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dac_waddr <= dac_waddr_g2b_s;
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dac_addr_diff <= dac_addr_diff_s[ADDRESS_WIDTH-1:0];
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if (dac_addr_diff > 0) begin
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dac_mem_ready <= 1'b1;
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end else begin
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dac_mem_ready <= 1'b0;
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end
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end
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end
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ad_g2b #(
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.DATA_WIDTH (ADDRESS_WIDTH))
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i_dac_waddr_g2b (
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.din (dac_waddr_m2),
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.dout (dac_waddr_g2b_s));
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// sync lastaddr to dac clock domain
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always @(posedge dac_clk) begin
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if (dac_rst_int_s == 1'b1) begin
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dac_lastaddr_m1 <= 1'b0;
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dac_lastaddr_m2 <= 1'b0;
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dac_xfer_out_fifo_m1 <= 1'b0;
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dac_xfer_out_fifo <= 1'b0;
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dac_xfer_out_fifo_d <= 1'b0;
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end else begin
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dac_lastaddr_m1 <= dma_lastaddr_g;
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dac_lastaddr_m2 <= dac_lastaddr_m1;
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dac_lastaddr <= dac_lastaddr_g2b_s;
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dac_xfer_out_fifo_m1 <= dma_xfer_out_fifo;
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dac_xfer_out_fifo <= dac_xfer_out_fifo_m1;
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if (dac_valid)
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dac_xfer_out_fifo_d <= dac_xfer_out_fifo;
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end
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end
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ad_g2b #(
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.DATA_WIDTH (ADDRESS_WIDTH))
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i_dac_lastaddr_g2b (
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.din (dac_lastaddr_m2),
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.dout (dac_lastaddr_g2b_s));
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// generate dac read address
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assign dac_mem_ren_s = (dac_bypass == 1'b1) ? (dac_valid & dac_mem_ready) :
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(dac_valid & dac_xfer_out_fifo);
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always @(posedge dac_clk) begin
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if (dac_rst_int_s == 1'b1) begin
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dac_raddr <= 'b0;
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end else begin
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if (dac_mem_ren_s == 1'b1) begin
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if (dac_lastaddr == 'b0 || dac_raddr != dac_lastaddr) begin
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dac_raddr <= dac_raddr + 1'b1;
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end else begin
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dac_raddr <= 'b0;
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end
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end
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end
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end
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// memory instantiation
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ad_mem #(
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.ADDRESS_WIDTH (ADDRESS_WIDTH),
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.DATA_WIDTH (DATA_WIDTH))
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i_mem_fifo (
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.clka (dma_clk),
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.wea (dma_wren_s),
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.addra (dma_waddr),
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.dina (dma_data),
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.clkb (dac_clk),
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.reb (1'b1),
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.addrb (dac_raddr),
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.doutb (dac_data_fifo_s));
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// define underflow
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// underflow make sense just if bypass is enabled
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always @(posedge dac_clk) begin
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if (dac_rst_int_s == 1'b1) begin
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dac_dunf <= 1'b0;
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end else begin
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dac_dunf <= (dac_bypass == 1'b1) ? (dac_valid & dac_xfer_req & ~dac_mem_ren_s) : 1'b0;
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end
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end
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// bypass logic
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util_dacfifo_bypass #(
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.DAC_DATA_WIDTH (DATA_WIDTH),
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.DMA_DATA_WIDTH (DATA_WIDTH)
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) i_dacfifo_bypass (
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.dma_clk(dma_clk),
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.dma_data(dma_data),
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.dma_ready(dma_ready),
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.dma_ready_out(dma_ready_bypass_s),
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.dma_valid(dma_valid),
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.dma_xfer_req(dma_xfer_req),
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.dac_clk(dac_clk),
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.dac_rst(dac_rst),
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.dac_valid(dac_valid),
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.dac_data(dac_data_bypass_s),
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.dac_dunf(dac_dunf_bypass_s)
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);
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always @(posedge dma_clk) begin
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dma_bypass_m1 <= bypass;
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dma_bypass <= dma_bypass_m1;
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end
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always @(posedge dac_clk) begin
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dac_bypass_m1 <= bypass;
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dac_bypass <= dac_bypass_m1;
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end
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// the util_dacfifo is always ready for the DMA
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always @(posedge dma_clk) begin
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dma_ready <= (dma_bypass == 1'b1) ? dma_ready_bypass_s : 1'b1;
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end
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always @(posedge dac_clk) begin
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if (dac_valid) begin
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dac_data <= (dac_bypass == 1'b1) ? dac_data_bypass_s : dac_data_fifo_s;
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end
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// this signal along with the dac_valid validate the data coming out from the buffer
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dac_xfer_out <= (dac_bypass == 1'b1) ? dac_xfer_req : dac_xfer_out_fifo_d;
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end
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endmodule
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