AndreiGrozav 64f5a99c63 axi_adc_trigger: Add and 1 extra delay ... The extra delay was added on the trigger and data paths to compensate for the logic analyzer changes. The extra delay will be also seen on the m2k daisy chain. The delay between devices will be increased from 3 to 4 samples delay.		2019-10-28 13:13:10 +00:00
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Makefile	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
axi_adc_trigger.v	axi_adc_trigger: Add and 1 extra delay	2019-10-28 13:13:10 +00:00
axi_adc_trigger_constr.xdc	constraints: up_xfer_cntrl and up_xfer_status have its own constraints	2018-04-11 15:09:54 +03:00
axi_adc_trigger_ip.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
axi_adc_trigger_reg.v	axi_adc_trigger: Add cascade support.	2019-08-22 18:06:10 +03:00