161 lines
5.1 KiB
Verilog
161 lines
5.1 KiB
Verilog
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_adc (
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clk,
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// control ports
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control,
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status,
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// FIFO interface
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src_adc_enable,
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src_adc_valid,
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src_adc_data,
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dst_adc_enable,
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dst_adc_valid,
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dst_adc_data
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);
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localparam RP_ID = 8'hA1;
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parameter CHANNEL_ID = 0;
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input clk;
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input [31:0] control;
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output [31:0] status;
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input src_adc_enable;
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input src_adc_valid;
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input [15:0] src_adc_data;
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output dst_adc_enable;
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output dst_adc_valid;
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output [15:0] dst_adc_data;
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reg dst_adc_enable;
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reg dst_adc_valid;
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reg [15:0] dst_adc_data;
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reg [31:0] status = 0;
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reg [15:0] adc_pn_data = 0;
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reg [ 3:0] mode;
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reg [ 3:0] channel_sel;
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wire adc_dvalid;
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wire [15:0] adc_pn_data_s;
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wire adc_pn_oos_s;
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wire adc_pn_err_s;
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// prbs function
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function [15:0] pn;
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input [15:0] din;
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reg [15:0] dout;
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begin
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dout[15] = din[14] ^ din[15];
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dout[14] = din[13] ^ din[14];
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dout[13] = din[12] ^ din[13];
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dout[12] = din[11] ^ din[12];
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dout[11] = din[10] ^ din[11];
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dout[10] = din[ 9] ^ din[10];
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dout[ 9] = din[ 8] ^ din[ 9];
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dout[ 8] = din[ 7] ^ din[ 8];
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dout[ 7] = din[ 6] ^ din[ 7];
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dout[ 6] = din[ 5] ^ din[ 6];
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dout[ 5] = din[ 4] ^ din[ 5];
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dout[ 4] = din[ 3] ^ din[ 4];
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dout[ 3] = din[ 2] ^ din[ 3];
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dout[ 2] = din[ 1] ^ din[ 2];
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dout[ 1] = din[ 0] ^ din[ 1];
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dout[ 0] = din[14] ^ din[15] ^ din[ 0];
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pn = dout;
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end
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endfunction
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assign adc_dvalid = src_adc_enable & src_adc_valid;
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always @(posedge clk) begin
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channel_sel <= control[3:0];
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mode <= control[7:4];
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end
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// prbs generation
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always @(posedge clk) begin
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if(adc_dvalid == 1'b1) begin
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adc_pn_data <= pn(adc_pn_data_s);
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end
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end
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assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? src_adc_ddata : adc_pn_data;
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ad_pnmon #(
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.DATA_WIDTH(32)
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) i_pn_mon (
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.adc_clk(clk),
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.adc_valid_in(adc_dvalid),
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.adc_data_in(src_adc_ddata),
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.adc_data_pn(adc_pn_data),
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.adc_pn_oos(adc_pn_oos_s),
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.adc_pn_err(adc_pn_err_s));
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// rx path are passed through on test mode
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always @(posedge clk) begin
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dst_adc_enable <= src_adc_enable;
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dst_adc_data <= src_adc_data;
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dst_adc_valid <= src_adc_valid;
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end
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// setup status bits for gpio_out
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always @(posedge clk) begin
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if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
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status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
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end else begin
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status <= {24'h0, RP_ID};
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end
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end
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endmodule
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