239 lines
8.0 KiB
Tcl
239 lines
8.0 KiB
Tcl
###################################################################################################
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###################################################################################################
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# keep interface-mess out of the way - keeping it pretty is a waste of time
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proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
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if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "input"])} {
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add_interface if_${name} clock sink
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add_interface_port if_${name} ${name} clk ${dir} ${width}
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return
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}
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if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "output"])} {
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add_interface if_${name} clock source
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add_interface_port if_${name} ${name} clk ${dir} ${width}
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return
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}
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if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "input"])} {
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add_interface if_${name} reset sink
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add_interface_port if_${name} ${name} reset ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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return
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}
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if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "output"])} {
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add_interface if_${name} reset source
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add_interface_port if_${name} ${name} reset ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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set_interface_property if_${name} associatedResetSinks ${arg_2}
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return
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}
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if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "input"])} {
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add_interface if_${name} reset sink
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add_interface_port if_${name} ${name} reset_n ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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return
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}
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if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "output"])} {
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add_interface if_${name} reset source
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add_interface_port if_${name} ${name} reset_n ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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set_interface_property if_${name} associatedResetSinks ${arg_2}
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return
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}
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if {([string equal -nocase ${type} "intr"]) && ([string equal -nocase ${dir} "output"])} {
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add_interface if_${name} interrupt source
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add_interface_port if_${name} ${name} irq ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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return
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}
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set remap $arg_1
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if {$arg_1 eq ""} {
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set remap $name
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}
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if {[string equal -nocase ${type} "signal"]} {
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add_interface if_${name} conduit end
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add_interface_port if_${name} ${name} ${remap} ${dir} ${width}
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return
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}
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}
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proc ad_conduit {if_name if_port port dir width} {
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add_interface $if_name conduit end
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add_interface_port $if_name $port $if_port $dir $width
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}
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proc ad_generate_module_inst { inst_name mark source_file target_file } {
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set fp_source [open $source_file "r"]
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set fp_target [open $target_file "w+"]
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fconfigure $fp_source -buffering line
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while { [gets $fp_source data] >= 0 } {
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# update the required module name
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regsub $inst_name $data "&_$mark" data
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puts $data
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puts $fp_target $data
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}
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close $fp_source
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close $fp_target
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}
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###################################################################################################
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###################################################################################################
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proc ad_ip_create {pname pdesc {pelabfunction ""} {pcomposefunction ""}} {
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set_module_property NAME $pname
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set_module_property DESCRIPTION $pdesc
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME $pname
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if {$pelabfunction ne ""} {
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set_module_property ELABORATION_CALLBACK $pelabfunction
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}
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if {$pcomposefunction ne ""} {
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set_module_property COMPOSITION_CALLBACK $pcomposefunction
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}
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}
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###################################################################################################
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###################################################################################################
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proc ad_ip_parameter {pname ptype pdefault} {
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if {$pname eq "DEVICE_FAMILY"} {
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add_parameter DEVICE_FAMILY STRING
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
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set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
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set_parameter_property DEVICE_FAMILY ENABLED false
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return
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}
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add_parameter $pname $ptype $pdefault
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set_parameter_property $pname HDL_PARAMETER true
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set_parameter_property $pname ENABLED true
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}
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###################################################################################################
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###################################################################################################
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proc ad_ip_addfile {pname pfile} {
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set pmodule [file tail $pfile]
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regsub {\..$} $pmodule {} mname
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if {$pname eq $mname} {
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add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
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return
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}
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set ptype [file extension $pfile]
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if {$ptype eq ".v"} {
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add_fileset_file $pmodule VERILOG PATH $pfile
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return
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}
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if {$ptype eq ".sdc"} {
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add_fileset_file $pmodule SDC PATH $pfile
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return
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}
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}
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proc ad_ip_files {pname pfiles {pfunction ""}} {
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add_fileset quartus_synth QUARTUS_SYNTH $pfunction ""
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set_fileset_property quartus_synth TOP_LEVEL $pname
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foreach pfile $pfiles {
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ad_ip_addfile $pname $pfile
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}
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add_fileset quartus_sim SIM_VERILOG $pfunction ""
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set_fileset_property quartus_sim TOP_LEVEL $pname
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foreach pfile $pfiles {
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ad_ip_addfile $pname $pfile
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}
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}
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###################################################################################################
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###################################################################################################
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proc ad_ip_intf_s_axi {aclk arstn} {
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add_interface s_axi_clock clock end
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add_interface_port s_axi_clock ${aclk} clk Input 1
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add_interface s_axi_reset reset end
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set_interface_property s_axi_reset associatedClock s_axi_clock
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add_interface_port s_axi_reset ${arstn} reset_n Input 1
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add_interface s_axi axi4lite end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input 16
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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add_interface_port s_axi s_axi_wdata wdata Input 32
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add_interface_port s_axi s_axi_wstrb wstrb Input 4
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add_interface_port s_axi s_axi_wready wready Output 1
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add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input 16
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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}
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###################################################################################################
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###################################################################################################
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proc ad_ip_modfile {ifile ofile flist} {
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global ad_hdl_dir
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set srcfile [open ${ad_hdl_dir}/library/altera/common/${ifile} r]
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set dstfile [open ${ofile} w]
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regsub {\..$} $ifile {} imodule
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regsub {\..$} $ofile {} omodule
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while {[gets $srcfile srcline] >= 0} {
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regsub __${imodule}__ $srcline $omodule dstline
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set index 0
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foreach fword $flist {
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incr index
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regsub __${imodule}_${index}__ $dstline $fword dstline
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}
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puts $dstfile $dstline
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}
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close $srcfile
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close $dstfile
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ad_ip_addfile ad_ip_addfile $ofile
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}
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###################################################################################################
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###################################################################################################
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