261 lines
8.5 KiB
Verilog
261 lines
8.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2016(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dacfifo_rd (
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// xfer last for read/write synchronization
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axi_xfer_req,
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axi_last_raddr,
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axi_last_beats,
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// axi read address and read data channels
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axi_clk,
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axi_resetn,
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axi_arvalid,
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axi_arid,
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axi_arburst,
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axi_arlock,
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axi_arcache,
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axi_arprot,
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axi_arqos,
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axi_aruser,
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axi_arlen,
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axi_arsize,
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axi_araddr,
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axi_arready,
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axi_rvalid,
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axi_rid,
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axi_ruser,
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axi_rresp,
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axi_rlast,
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axi_rdata,
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axi_rready,
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// axi status
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axi_rerror,
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// fifo interface
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axi_dvalid,
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axi_ddata,
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axi_dready,
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axi_dlast);
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// parameters
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parameter AXI_DATA_WIDTH = 512;
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parameter AXI_SIZE = 2;
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parameter AXI_LENGTH = 15;
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parameter AXI_ADDRESS = 32'h00000000;
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localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
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localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;
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// xfer last for read/write synchronization
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input axi_xfer_req;
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input [31:0] axi_last_raddr;
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input [ 3:0] axi_last_beats;
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// axi interface
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input axi_clk;
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input axi_resetn;
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output axi_arvalid;
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output [ 3:0] axi_arid;
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output [ 1:0] axi_arburst;
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output axi_arlock;
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output [ 3:0] axi_arcache;
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output [ 2:0] axi_arprot;
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output [ 3:0] axi_arqos;
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output [ 3:0] axi_aruser;
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output [ 7:0] axi_arlen;
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output [ 2:0] axi_arsize;
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output [31:0] axi_araddr;
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input axi_arready;
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input axi_rvalid;
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input [ 3:0] axi_rid;
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input [ 3:0] axi_ruser;
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input [ 1:0] axi_rresp;
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input axi_rlast;
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input [(AXI_DATA_WIDTH-1):0] axi_rdata;
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output axi_rready;
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// axi status
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output axi_rerror;
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// fifo interface
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output axi_dvalid;
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output [(AXI_DATA_WIDTH-1):0] axi_ddata;
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input axi_dready;
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output axi_dlast;
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// internal registers
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reg axi_rnext = 1'b0;
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reg axi_ractive = 1'b0;
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reg axi_arvalid = 1'b0;
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reg [ 31:0] axi_araddr = 32'b0;
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reg [ 31:0] axi_araddr_prev = 32'b0;
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reg [(AXI_DATA_WIDTH-1):0] axi_ddata = 'b0;
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reg axi_dvalid = 1'b0;
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reg axi_dlast = 1'b0;
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reg axi_rready = 1'b0;
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reg axi_rerror = 1'b0;
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reg [ 1:0] axi_xfer_req_m = 2'b0;
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reg [ 4:0] axi_last_beats_cntr = 16'b0;
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// internal signals
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wire axi_ready_s;
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wire axi_xfer_req_init;
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wire axi_dvalid_s;
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wire axi_dlast_s;
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wire [ 4:0] axi_last_beats_s;
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assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_rnext <= 1'b0;
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axi_ractive <= 1'b0;
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axi_xfer_req_m <= 2'b0;
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end else begin
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if (axi_ractive == 1'b1) begin
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axi_rnext <= 1'b0;
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if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
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axi_ractive <= 1'b0;
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end
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end else if ((axi_ready_s == 1'b1)) begin
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axi_rnext <= axi_xfer_req;
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axi_ractive <= axi_xfer_req;
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end
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axi_xfer_req_m <= {axi_xfer_req_m[0], axi_xfer_req};
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end
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end
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assign axi_xfer_req_init = axi_xfer_req_m[0] & ~axi_xfer_req_m[1];
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always @(posedge axi_clk) begin
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if ((axi_resetn == 1'b0) || (axi_xfer_req == 1'b0)) begin
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axi_last_beats_cntr <= 0;
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end else begin
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if ((axi_rready == 1'b1) && (axi_rvalid == 1'b1)) begin
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axi_last_beats_cntr <= (axi_rlast == 1'b1) ? 0 : axi_last_beats_cntr + 1;
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end
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end
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end
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// address channel
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assign axi_arid = 4'b0000;
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assign axi_arburst = 2'b01;
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assign axi_arlock = 1'b0;
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assign axi_arcache = 4'b0010;
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assign axi_arprot = 3'b000;
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assign axi_arqos = 4'b0000;
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assign axi_aruser = 4'b0001;
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assign axi_arlen = AXI_LENGTH;
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assign axi_arsize = AXI_SIZE;
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_arvalid <= 'd0;
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axi_araddr <= AXI_ADDRESS;
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axi_araddr_prev <= AXI_ADDRESS;
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end else begin
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if (axi_arvalid == 1'b1) begin
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if (axi_arready == 1'b1) begin
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axi_arvalid <= 1'b0;
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end
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end else begin
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if (axi_rnext == 1'b1) begin
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axi_arvalid <= 1'b1;
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end
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end
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if ((axi_xfer_req == 1'b1) &&
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(axi_arvalid == 1'b1) &&
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(axi_arready == 1'b1)) begin
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axi_araddr <= (axi_araddr >= axi_last_raddr) ? AXI_ADDRESS : axi_araddr + AXI_AWINCR;
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axi_araddr_prev <= axi_araddr;
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end
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end
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end
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// read data channel
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assign axi_last_beats_s = {1'b0, axi_last_beats} - 1;
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assign axi_dvalid_s = ((axi_last_beats_cntr > axi_last_beats_s) && (axi_araddr_prev == axi_last_raddr)) ? 0 : axi_rvalid & axi_rready;
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assign axi_dlast_s = (axi_araddr_prev == axi_last_raddr) ? 1 : 0;
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_ddata <= 'd0;
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axi_rready <= 1'b0;
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axi_dvalid <= 1'b0;
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end else begin
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axi_ddata <= axi_rdata;
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axi_dvalid <= axi_dvalid_s;
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axi_dlast <= axi_dlast_s;
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if (axi_xfer_req == 1'b1) begin
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axi_rready <= axi_rvalid;
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end
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end
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end
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_rerror <= 'd0;
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end else begin
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axi_rerror <= axi_rvalid & axi_rresp[1];
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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