569 lines
20 KiB
Verilog
569 lines
20 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2016(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dacfifo_wr (
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// dma fifo interface
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dma_clk,
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dma_data,
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dma_ready,
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dma_valid,
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// request and syncronizaiton
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dma_xfer_req,
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dma_xfer_last,
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dma_last_beats,
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// syncronization for the read side
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axi_last_addr,
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axi_last_beats,
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axi_xfer_out,
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// axi write address, write data and write response channels
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axi_clk,
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axi_resetn,
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axi_awvalid,
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axi_awid,
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axi_awburst,
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axi_awlock,
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axi_awcache,
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axi_awprot,
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axi_awqos,
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axi_awuser,
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axi_awlen,
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axi_awsize,
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axi_awaddr,
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axi_awready,
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axi_wvalid,
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axi_wdata,
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axi_wstrb,
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axi_wlast,
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axi_wuser,
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axi_wready,
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axi_bvalid,
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axi_bid,
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axi_bresp,
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axi_buser,
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axi_bready,
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axi_werror);
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// parameters
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parameter AXI_DATA_WIDTH = 512;
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parameter DMA_DATA_WIDTH = 64;
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parameter AXI_SIZE = 6; // axi_awsize format
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parameter AXI_LENGTH = 15; // axi_awlength format
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parameter AXI_ADDRESS = 32'h00000000;
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parameter AXI_ADDRESS_LIMIT = 32'h00000000;
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parameter DMA_MEM_ADDRESS_WIDTH = 8;
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// for the syncronization buffer
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localparam MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16
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localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH :
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(MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) :
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(MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) :
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(MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) :
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(DMA_MEM_ADDRESS_WIDTH - 4);
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// for the AXI interface
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localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
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localparam DMA_BYTE_WIDTH = DMA_DATA_WIDTH/8;
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localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;
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localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4;
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// dma fifo interface
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input dma_clk;
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input [(DMA_DATA_WIDTH-1):0] dma_data;
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output dma_ready;
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input dma_valid;
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input dma_xfer_req;
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input dma_xfer_last;
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output [ 3:0] dma_last_beats;
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output [31:0] axi_last_addr;
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output [ 3:0] axi_last_beats;
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output axi_xfer_out;
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// axi interface
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input axi_clk;
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input axi_resetn;
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output axi_awvalid;
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output [ 3:0] axi_awid;
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output [ 1:0] axi_awburst;
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output axi_awlock;
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output [ 3:0] axi_awcache;
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output [ 2:0] axi_awprot;
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output [ 3:0] axi_awqos;
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output [ 3:0] axi_awuser;
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output [ 7:0] axi_awlen;
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output [ 2:0] axi_awsize;
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output [31:0] axi_awaddr;
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input axi_awready;
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output axi_wvalid;
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output [(AXI_DATA_WIDTH-1):0] axi_wdata;
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output [(AXI_BYTE_WIDTH-1):0] axi_wstrb;
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output axi_wlast;
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output [ 3:0] axi_wuser;
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input axi_wready;
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input axi_bvalid;
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input [ 3:0] axi_bid;
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input [ 1:0] axi_bresp;
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input [ 3:0] axi_buser;
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output axi_bready;
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output axi_werror;
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// registers
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reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;
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reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;
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reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_addr_diff = 'd0;
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reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0;
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reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0;
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reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0;
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reg dma_ready = 1'b0;
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reg dma_rst_m1 = 1'b0;
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reg dma_rst_m2 = 1'b0;
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reg [ 2:0] dma_mem_last_read_toggle_m = 3'b0;
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reg dma_xfer_req_d = 1'b0;
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reg [ 3:0] dma_last_beats = 4'b0;
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reg [ 4:0] axi_xfer_req_m = 3'b0;
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reg [ 4:0] axi_xfer_last_m = 3'b0;
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reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m1 = 'b0;
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reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2 = 'b0;
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reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'b0;
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reg axi_mem_rvalid = 1'b0;
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reg axi_mem_rvalid_d = 1'b0;
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reg axi_mem_last = 1'b0;
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reg axi_mem_last_d = 1'b0;
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reg [(AXI_DATA_WIDTH-1):0] axi_mem_rdata = 'b0;
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reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0;
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reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_g = 'd0;
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reg axi_mem_read_en = 1'b0;
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reg axi_mem_read_en_d = 1'b0;
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reg axi_mem_read_en_delay = 1'b0;
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reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'b0;
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reg axi_mem_last_read_toggle = 1'b0;
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reg axi_reset = 1'b0;
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reg axi_xfer_out = 1'b0;
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reg [31:0] axi_last_addr = 32'b0;
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reg [ 3:0] axi_last_beats = 15'b0;
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reg axi_awvalid = 1'b0;
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reg [31:0] axi_awaddr = 32'b0;
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reg axi_xfer_init = 1'b0;
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reg axi_werror = 1'b0;
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reg [ 3:0] axi_wvalid_counter = 4'b0;
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reg axi_endof_transaction = 1'b0;
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reg axi_endof_transaction_d = 1'b0;
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// internal signals
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wire [(DMA_MEM_ADDRESS_WIDTH):0] dma_mem_addr_diff_s;
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wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;
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wire dma_mem_last_read_s;
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wire dma_xfer_init;
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wire dma_mem_wea_s;
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wire dma_rst_s;
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wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;
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wire [AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;
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wire [(AXI_DATA_WIDTH-1):0] axi_mem_rdata_s;
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wire axi_mem_rvalid_s;
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wire axi_mem_last_s;
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wire axi_waddr_ready_s;
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wire axi_wready_s;
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// binary to grey conversion
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function [7:0] b2g;
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input [7:0] b;
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reg [7:0] g;
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begin
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g[7] = b[7];
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g[6] = b[7] ^ b[6];
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g[5] = b[6] ^ b[5];
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g[4] = b[5] ^ b[4];
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g[3] = b[4] ^ b[3];
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g[2] = b[3] ^ b[2];
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g[1] = b[2] ^ b[1];
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g[0] = b[1] ^ b[0];
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b2g = g;
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end
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endfunction
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// grey to binary conversion
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function [7:0] g2b;
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input [7:0] g;
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reg [7:0] b;
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begin
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b[7] = g[7];
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b[6] = b[7] ^ g[6];
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b[5] = b[6] ^ g[5];
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b[4] = b[5] ^ g[4];
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b[3] = b[4] ^ g[3];
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b[2] = b[3] ^ g[2];
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b[1] = b[2] ^ g[1];
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b[0] = b[1] ^ g[0];
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g2b = b;
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end
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endfunction
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// Instantiations
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// An asymmetric memory to transfer data from DMAC interface to AXI Memory Map
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// interface
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH),
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.A_DATA_WIDTH (DMA_DATA_WIDTH),
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.B_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH),
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.B_DATA_WIDTH (AXI_DATA_WIDTH))
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i_mem_asym (
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.clka (dma_clk),
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.wea (dma_mem_wea_s),
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.addra (dma_mem_waddr),
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.dina (dma_data),
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.clkb (axi_clk),
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.addrb (axi_mem_raddr),
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.doutb (axi_mem_rdata_s));
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ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
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.clk (axi_clk),
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.rst (axi_reset),
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.valid (axi_mem_rvalid_d),
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.last (axi_mem_last_d),
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.data (axi_mem_rdata),
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.inf_valid (axi_wvalid),
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.inf_last (axi_wlast),
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.inf_data (axi_wdata),
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.inf_ready (axi_wready));
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// fifo needs a reset
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_reset <= 1'b1;
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end else begin
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axi_reset <= 1'b0;
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end
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end
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always @(posedge dma_clk) begin
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dma_rst_m1 <= ~axi_resetn;
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dma_rst_m2 <= dma_rst_m1;
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end
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assign dma_rst_s = dma_rst_m2;
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// DMA beat counter
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assign dma_xfer_init = dma_xfer_req & ~dma_xfer_req_d;
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always @(posedge dma_clk) begin
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dma_xfer_req_d <= dma_xfer_req;
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if ((dma_rst_s == 1'b1) || (dma_xfer_init == 1'b1)) begin
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dma_last_beats <= 4'b0;
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end else begin
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if ((dma_ready == 1'b1) && (dma_valid == 1'b1)) begin
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dma_last_beats <= (dma_last_beats < MEM_RATIO-1) ? dma_last_beats + 1 : 0;
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end
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end
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end
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// Write address generation for the asymmetric memory
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assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
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assign dma_mem_raddr_s = (MEM_RATIO == 1) ? dma_mem_raddr :
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(MEM_RATIO == 2) ? {dma_mem_raddr, 1'b0} :
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(MEM_RATIO == 4) ? {dma_mem_raddr, 2'b0} :
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(MEM_RATIO == 8) ? {dma_mem_raddr, 3'b0} :
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{dma_mem_raddr, 4'b0};
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assign dma_mem_last_read_s = dma_mem_last_read_toggle_m[2] ^ dma_mem_last_read_toggle_m[1];
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assign dma_mem_wea_s = dma_xfer_req & dma_valid;
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always @(posedge dma_clk) begin
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if (dma_rst_s == 1'b1) begin
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dma_mem_waddr <= 'h0;
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dma_mem_waddr_g <= 'h0;
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dma_mem_last_read_toggle_m <= 3'b0;
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end else begin
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dma_mem_last_read_toggle_m = {dma_mem_last_read_toggle_m[1:0], axi_mem_last_read_toggle};
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if (dma_mem_wea_s == 1'b1) begin
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dma_mem_waddr <= dma_mem_waddr + 8'b1;
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if (dma_xfer_last == 1'b1) begin
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if (dma_last_beats != (MEM_RATIO - 1)) begin
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dma_mem_waddr <= dma_mem_waddr + (MEM_RATIO - dma_last_beats);
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end
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end
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end
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if (dma_mem_last_read_s == 1'b1) begin
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dma_mem_waddr <= 'h0;
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end
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dma_mem_waddr_g <= b2g(dma_mem_waddr);
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end
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end
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// The memory module request data until reaches the high threshold.
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always @(posedge dma_clk) begin
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if (dma_rst_s == 1'b1) begin
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dma_mem_addr_diff <= 'b0;
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dma_mem_raddr_m1 <= 'b0;
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dma_mem_raddr_m2 <= 'b0;
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dma_mem_raddr <= 'b0;
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dma_ready <= 1'b0;
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end else begin
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dma_mem_raddr_m1 <= axi_mem_raddr_g;
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dma_mem_raddr_m2 <= dma_mem_raddr_m1;
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dma_mem_raddr <= g2b(dma_mem_raddr_m2);
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dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
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if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
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dma_ready <= 1'b0;
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end else begin
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dma_ready <= 1'b1;
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end
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end
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end
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// Read address generation for the asymmetric memory
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// CDC for the memory write address, xfer_req and xfer_last
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_xfer_req_m <= 4'b0;
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axi_xfer_last_m <= 5'b0;
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axi_xfer_init <= 1'b0;
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axi_mem_waddr_m1 <= 'b0;
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axi_mem_waddr_m2 <= 'b0;
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axi_mem_waddr <= 'b0;
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end else begin
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axi_xfer_req_m <= {axi_xfer_req_m[3:0], dma_xfer_req};
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axi_xfer_last_m <= {axi_xfer_last_m[3:0], dma_xfer_last};
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axi_xfer_init = ~axi_xfer_req_m[2] & axi_xfer_req_m[1];
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axi_mem_waddr_m1 <= dma_mem_waddr_g;
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axi_mem_waddr_m2 <= axi_mem_waddr_m1;
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axi_mem_waddr <= g2b(axi_mem_waddr_m2);
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end
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end
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// check if the AXI write channel is ready
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assign axi_wready_s = ~axi_wvalid | axi_wready;
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// check if there is enough data in the asymmetric memory
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assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr :
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(MEM_RATIO == 2) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):1] :
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(MEM_RATIO == 4) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):2] :
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(MEM_RATIO == 8) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):3] :
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axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):4];
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assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr_s} - axi_mem_raddr;
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_endof_transaction <= 1'b0;
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axi_endof_transaction_d <= 1'b0;
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axi_mem_addr_diff <= 'b0;
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end else begin
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axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0];
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axi_endof_transaction_d <= axi_endof_transaction;
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if ((axi_xfer_req_m[4] == 1'b1) && (axi_xfer_last_m[4] == 1'b1) && (axi_xfer_last_m[3] == 1'b0)) begin
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axi_endof_transaction <= 1'b1;
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end else if((axi_endof_transaction == 1'b1) && (axi_wlast == 1'b1) && ((axi_mem_addr_diff == 0) || (axi_mem_addr_diff > AXI_LENGTH))) begin
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axi_endof_transaction <= 1'b0;
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end
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end
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end
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// The asymmetric memory have to have enough data for at least one AXI burst,
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// before the controller start an AXI write transaction.
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_mem_read_en <= 1'b0;
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axi_mem_read_en_d <= 1'b0;
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axi_mem_read_en_delay <= 1'b0;
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axi_mem_addr_diff <= 'b0;
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end else begin
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axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0];
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if ((axi_mem_read_en == 1'b0) && (axi_mem_read_en_delay == 1'b0)) begin
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if (((axi_xfer_req_m[2] == 1'b1) && (axi_mem_addr_diff > AXI_LENGTH)) ||
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((axi_endof_transaction == 1'b1) && (axi_mem_addr_diff > AXI_LENGTH)) ||
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((axi_endof_transaction == 1'b1) && (axi_mem_addr_diff > 0))) begin
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axi_mem_read_en <= 1'b1;
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end
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end else if (axi_mem_last_s == 1'b1) begin
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axi_mem_read_en <= 1'b0;
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axi_mem_read_en_delay <= 1;
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end
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if (axi_wlast == 1'b1) begin
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axi_mem_read_en_delay <= 0;
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end
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axi_mem_read_en_d <= axi_mem_read_en;
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end
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end
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|
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assign axi_mem_rvalid_s = axi_mem_read_en & axi_wready_s;
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assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_rvalid_s : 1'b0;
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|
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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axi_mem_rvalid <= 1'b0;
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axi_mem_rvalid_d <= 1'b0;
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axi_mem_last <= 1'b0;
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axi_mem_last_d <= 1'b0;
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axi_mem_rdata <= 'b0;
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axi_mem_raddr <= 'b0;
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axi_wvalid_counter <= 4'b0;
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axi_mem_last_read_toggle <= 1'b1;
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axi_mem_raddr_g <= 8'b0;
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end else begin
|
|
axi_mem_rvalid <= axi_mem_rvalid_s;
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axi_mem_rvalid_d <= axi_mem_rvalid;
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axi_mem_last <= axi_mem_last_s;
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axi_mem_last_d <= axi_mem_last;
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axi_mem_rdata <= axi_mem_rdata_s;
|
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if (axi_mem_rvalid_s == 1'b1) begin
|
|
axi_mem_raddr <= axi_mem_raddr + 1;
|
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axi_wvalid_counter <= ((axi_wvalid_counter == axi_awlen) || (axi_xfer_init == 1'b1)) ? 4'b0 : axi_wvalid_counter + 1;
|
|
end
|
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if ((axi_endof_transaction == 1'b0) && (axi_endof_transaction_d == 1'b1)) begin
|
|
axi_mem_raddr <= 'b0;
|
|
axi_mem_last_read_toggle <= ~axi_mem_last_read_toggle;
|
|
end
|
|
axi_mem_raddr_g <= b2g(axi_mem_raddr);
|
|
end
|
|
end
|
|
|
|
// AXI Memory Map interface write address channel
|
|
|
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assign axi_awid = 4'b0000;
|
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assign axi_awburst = 2'b01;
|
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assign axi_awlock = 1'b0;
|
|
assign axi_awcache = 4'b0010;
|
|
assign axi_awprot = 3'b000;
|
|
assign axi_awqos = 4'b0000;
|
|
assign axi_awuser = 4'b0001;
|
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assign axi_awlen = AXI_LENGTH;
|
|
assign axi_awsize = AXI_SIZE;
|
|
|
|
assign axi_waddr_ready_s = axi_mem_read_en & ~axi_mem_read_en_d;
|
|
|
|
always @(posedge axi_clk) begin
|
|
if (axi_resetn == 1'b0) begin
|
|
axi_awvalid <= 'd0;
|
|
axi_awaddr <= AXI_ADDRESS;
|
|
axi_last_addr <= AXI_ADDRESS;
|
|
axi_xfer_out <= 1'b0;
|
|
end else begin
|
|
if (axi_awvalid == 1'b1) begin
|
|
if (axi_awready == 1'b1) begin
|
|
axi_awvalid <= 1'b0;
|
|
end
|
|
end else begin
|
|
if (axi_waddr_ready_s == 1'b1) begin
|
|
axi_awvalid <= 1'b1;
|
|
end
|
|
end
|
|
if (axi_xfer_init == 1'b1) begin
|
|
axi_awaddr <= (axi_xfer_out == 1'b1) ? AXI_ADDRESS : axi_last_addr;
|
|
axi_xfer_out <= 1'b0;
|
|
end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
|
|
axi_awaddr <= axi_awaddr + AXI_AWINCR;
|
|
end
|
|
if (axi_xfer_last_m[2] == 1'b1) begin
|
|
axi_xfer_out <= 1'b1;
|
|
end
|
|
if ((axi_awvalid == 1'b1) && (axi_endof_transaction == 1'b1)) begin
|
|
axi_last_addr <= axi_awaddr;
|
|
end
|
|
end
|
|
end
|
|
|
|
// write data channel controls
|
|
|
|
assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
|
|
assign axi_wuser = 4'b0000;
|
|
|
|
// response channel
|
|
|
|
assign axi_bready = 1'b1;
|
|
|
|
always @(posedge axi_clk) begin
|
|
if (axi_resetn == 1'b0) begin
|
|
axi_werror <= 'd0;
|
|
end else begin
|
|
axi_werror <= axi_bvalid & axi_bresp[1];
|
|
end
|
|
end
|
|
|
|
// AXI beat counter
|
|
|
|
always @(posedge axi_clk) begin
|
|
if(axi_resetn == 1'b0) begin
|
|
axi_last_beats <= 4'b0;
|
|
end else begin
|
|
if ((axi_endof_transaction == 1'b1) && (axi_awready == 1'b1) && (axi_awvalid == 1'b1)) begin
|
|
axi_last_beats <= axi_mem_addr_diff;
|
|
end else begin
|
|
axi_last_beats <= axi_last_beats;
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|