389 lines
10 KiB
Verilog
389 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr3_1_n,
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ddr3_1_p,
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ddr3_reset_n,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ras_n,
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ddr3_we_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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mdio_mdc,
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mdio_mdio_io,
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mii_rst_n,
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mii_col,
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mii_crs,
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mii_rx_clk,
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mii_rx_er,
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mii_rx_dv,
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mii_rxd,
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mii_tx_clk,
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mii_tx_en,
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mii_txd,
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fan_pwm,
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gpio_lcd,
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gpio_led,
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gpio_sw,
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iic_rstn,
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iic_scl,
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iic_sda,
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hdmi_out_clk,
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hdmi_hsync,
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hdmi_vsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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rx_ref_clk_p,
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rx_ref_clk_n,
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rx_sysref,
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rx_sync,
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rx_data_p,
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rx_data_n,
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spi_csn,
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spi_clk,
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spi_sdio);
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input uart_sin;
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output uart_sout;
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output [ 2:0] ddr3_1_n;
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output [ 1:0] ddr3_1_p;
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output ddr3_reset_n;
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output [13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output ddr3_ras_n;
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output ddr3_we_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output mdio_mdc;
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inout mdio_mdio_io;
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output mii_rst_n;
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input mii_col;
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input mii_crs;
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input mii_rx_clk;
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input mii_rx_er;
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input mii_rx_dv;
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input [ 3:0] mii_rxd;
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input mii_tx_clk;
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output mii_tx_en;
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output [ 3:0] mii_txd;
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output fan_pwm;
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inout [ 6:0] gpio_lcd;
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inout [ 7:0] gpio_led;
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inout [ 8:0] gpio_sw;
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output iic_rstn;
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inout iic_scl;
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inout iic_sda;
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output hdmi_out_clk;
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output hdmi_hsync;
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output hdmi_vsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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input rx_ref_clk_p;
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input rx_ref_clk_n;
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output rx_sysref;
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output rx_sync;
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input [ 3:0] rx_data_p;
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input [ 3:0] rx_data_n;
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output spi_csn;
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output spi_clk;
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inout spi_sdio;
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// internal registers
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reg dma_0_wr = 'd0;
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reg [63:0] dma_0_data = 'd0;
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reg dma_1_wr = 'd0;
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reg [63:0] dma_1_data = 'd0;
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// internal signals
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wire [14:0] gpio_i;
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wire [14:0] gpio_o;
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wire [14:0] gpio_t;
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wire rx_ref_clk;
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wire spi_miso;
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wire spi_mosi;
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wire adc_clk;
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wire [127:0] rx_gt_data;
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wire adc_0_enable_a;
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wire [31:0] adc_0_data_a;
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wire adc_0_enable_b;
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wire [31:0] adc_0_data_b;
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wire adc_1_enable_a;
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wire [31:0] adc_1_data_a;
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wire adc_1_enable_b;
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wire [31:0] adc_1_data_b;
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// pack & unpack here
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always @(posedge adc_clk) begin
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case ({adc_0_enable_b, adc_0_enable_a})
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2'b11: begin
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dma_0_wr <= 1'b1;
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dma_0_data[63:48] <= adc_0_data_b[31:16];
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dma_0_data[47:32] <= adc_0_data_a[31:16];
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dma_0_data[31:16] <= adc_0_data_b[15: 0];
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dma_0_data[15: 0] <= adc_0_data_a[15: 0];
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end
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2'b10: begin
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dma_0_wr <= ~dma_0_wr;
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dma_0_data[63:48] <= adc_0_data_b[31:16];
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dma_0_data[47:32] <= adc_0_data_b[15: 0];
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dma_0_data[31:16] <= dma_0_data[63:48];
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dma_0_data[15: 0] <= dma_0_data[47:32];
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end
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2'b01: begin
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dma_0_wr <= ~dma_0_wr;
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dma_0_data[63:48] <= adc_0_data_a[31:16];
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dma_0_data[47:32] <= adc_0_data_a[15: 0];
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dma_0_data[31:16] <= dma_0_data[63:48];
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dma_0_data[15: 0] <= dma_0_data[47:32];
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end
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default: begin
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dma_0_wr <= 1'b0;
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dma_0_data[63:48] <= 16'd0;
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dma_0_data[47:32] <= 16'd0;
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dma_0_data[31:16] <= 16'd0;
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dma_0_data[15: 0] <= 16'd0;
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end
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endcase
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end
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always @(posedge adc_clk) begin
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case ({adc_1_enable_b, adc_1_enable_a})
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2'b11: begin
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dma_1_wr <= 1'b1;
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dma_1_data[63:48] <= adc_1_data_b[31:16];
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dma_1_data[47:32] <= adc_1_data_a[31:16];
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dma_1_data[31:16] <= adc_1_data_b[15: 0];
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dma_1_data[15: 0] <= adc_1_data_a[15: 0];
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end
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2'b10: begin
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dma_1_wr <= ~dma_1_wr;
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dma_1_data[63:48] <= adc_1_data_b[31:16];
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dma_1_data[47:32] <= adc_1_data_b[15: 0];
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dma_1_data[31:16] <= dma_1_data[63:48];
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dma_1_data[15: 0] <= dma_1_data[47:32];
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end
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2'b01: begin
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dma_1_wr <= ~dma_1_wr;
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dma_1_data[63:48] <= adc_1_data_a[31:16];
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dma_1_data[47:32] <= adc_1_data_a[15: 0];
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dma_1_data[31:16] <= dma_1_data[63:48];
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dma_1_data[15: 0] <= dma_1_data[47:32];
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end
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default: begin
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dma_1_wr <= 1'b0;
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dma_1_data[63:48] <= 16'd0;
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dma_1_data[47:32] <= 16'd0;
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dma_1_data[31:16] <= 16'd0;
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dma_1_data[15: 0] <= 16'd0;
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end
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endcase
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end
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// instantiations
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IBUFDS_GTE2 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
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.dt (gpio_t),
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.di (gpio_o),
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.do (gpio_i),
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.dio (gpio_bd));
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assign spi_adc_clk = spi_clk;
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assign spi_clk_clk = spi_clk;
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fmcjesdadc1_spi i_fmcjesdadc1_spi (
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.spi_csn (spi_csn),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio));
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// instantiations
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system_wrapper i_system_wrapper (
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.ddr3_1_n (ddr3_1_n),
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.ddr3_1_p (ddr3_1_p),
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.fan_pwm (fan_pwm),
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.gpio_lcd_tri_io (gpio_lcd),
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.gpio_led_tri_io (gpio_led),
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.gpio_sw_tri_io (gpio_sw),
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.adc_0_data_a (adc_0_data_a),
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.adc_0_data_b (adc_0_data_b),
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.adc_0_enable_a (adc_0_enable_a),
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.adc_0_enable_b (adc_0_enable_b),
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.adc_0_valid_a (),
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.adc_0_valid_b (),
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.adc_1_data_a (adc_1_data_a),
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.adc_1_data_b (adc_1_data_b),
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.adc_1_enable_a (adc_1_enable_a),
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.adc_1_enable_b (adc_1_enable_b),
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.adc_1_valid_a (),
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.adc_1_valid_b (),
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.adc_clk (adc_clk),
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.dma_0_data (dma_0_data),
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.dma_0_sync (1'b1),
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.dma_0_wr (dma_0_wr),
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.dma_1_data (dma_1_data),
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.dma_1_sync (1'b1),
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.dma_1_wr (dma_1_wr),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.iic_rstn (iic_rstn),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio_io),
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.mii_col (mii_col),
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.mii_crs (mii_crs),
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.mii_rst_n (mii_rst_n),
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.mii_rx_clk (mii_rx_clk),
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.mii_rx_dv (mii_rx_dv),
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.mii_rx_er (mii_rx_er),
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.mii_rxd (mii_rxd),
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.mii_tx_clk (mii_tx_clk),
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.mii_tx_en (mii_tx_en),
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.mii_txd (mii_txd),
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.spdif (spdif),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.unc_int0 (1'b0),
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.unc_int1 (1'b0),
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.rx_data_n (rx_data_n),
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.rx_data_p (rx_data_p),
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.rx_gt_data (rx_gt_data),
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.rx_gt_data_0 (rx_gt_data[63:0]),
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.rx_gt_data_1 (rx_gt_data[127:64]),
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.rx_ref_clk (rx_ref_clk),
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.rx_sync (rx_sync),
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.rx_sysref (rx_sysref),
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.spi_clk_i (1'b0),
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.spi_clk_o (spi_clk),
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.spi_csn_i (1'b1),
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.spi_csn_o (spi_csn),
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.spi_sdi_i (spi_miso),
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.spi_sdo_i (1'b0),
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.spi_sdo_o (spi_mosi));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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