251 lines
7.3 KiB
Verilog
251 lines
7.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// MMCM with DRP and device specific
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`timescale 1ns/100ps
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module ad_mmcm_drp (
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// clocks
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clk,
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mmcm_rst,
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mmcm_clk_0,
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mmcm_clk_1,
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// drp interface
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up_clk,
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up_rstn,
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up_drp_sel,
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up_drp_wr,
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up_drp_addr,
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up_drp_wdata,
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up_drp_rdata,
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up_drp_ready,
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up_drp_locked);
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// parameters
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parameter MMCM_DEVICE_TYPE = 0;
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localparam MMCM_DEVICE_7SERIES = 0;
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localparam MMCM_DEVICE_VIRTEX6 = 1;
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parameter MMCM_CLKIN_PERIOD = 1.667;
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parameter MMCM_VCO_DIV = 6;
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parameter MMCM_VCO_MUL = 12.000;
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parameter MMCM_CLK0_DIV = 2.000;
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parameter MMCM_CLK1_DIV = 6;
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// clocks
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input clk;
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input mmcm_rst;
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output mmcm_clk_0;
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output mmcm_clk_1;
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// drp interface
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input up_clk;
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input up_rstn;
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input up_drp_sel;
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input up_drp_wr;
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input [11:0] up_drp_addr;
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input [15:0] up_drp_wdata;
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output [15:0] up_drp_rdata;
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output up_drp_ready;
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output up_drp_locked;
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// internal registers
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reg [15:0] up_drp_rdata = 'd0;
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reg up_drp_ready = 'd0;
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reg up_drp_locked_m1 = 'd0;
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reg up_drp_locked = 'd0;
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// internal signals
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wire bufg_fb_clk_s;
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wire mmcm_fb_clk_s;
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wire mmcm_clk_0_s;
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wire mmcm_clk_1_s;
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wire mmcm_locked_s;
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wire [15:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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// drp read and locked
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_drp_rdata <= 'd0;
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up_drp_ready <= 'd0;
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up_drp_locked_m1 <= 1'd0;
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up_drp_locked <= 1'd0;
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end else begin
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up_drp_rdata <= up_drp_rdata_s;
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up_drp_ready <= up_drp_ready_s;
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up_drp_locked_m1 <= mmcm_locked_s;
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up_drp_locked <= up_drp_locked_m1;
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end
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end
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// instantiations
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generate
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if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin
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MMCM_ADV #(
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.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.CLOCK_HOLD ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (MMCM_VCO_DIV),
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.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
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.REF_JITTER1 (0.010))
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i_mmcm (
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.CLKIN1 (clk),
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.CLKFBIN (bufg_fb_clk_s),
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.CLKFBOUT (mmcm_fb_clk_s),
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.CLKOUT0 (mmcm_clk_0_s),
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.CLKOUT1 (mmcm_clk_1_s),
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.LOCKED (mmcm_locked_s),
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.DCLK (up_clk),
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.DEN (up_drp_sel),
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.DADDR (up_drp_addr[6:0]),
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.DWE (up_drp_wr),
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.DI (up_drp_wdata),
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.DO (up_drp_rdata_s),
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.DRDY (up_drp_ready_s),
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.CLKFBOUTB (),
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.CLKOUT0B (),
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.CLKOUT1B (),
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.CLKOUT2 (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKIN2 (1'b0),
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.CLKINSEL (1'b1),
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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.CLKINSTOPPED (),
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.CLKFBSTOPPED (),
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.PWRDWN (1'b0),
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.RST (mmcm_rst));
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end
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if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
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MMCME2_ADV #(
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.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (MMCM_VCO_DIV),
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.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
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.REF_JITTER1 (0.010))
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i_mmcm (
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.CLKIN1 (clk),
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.CLKFBIN (bufg_fb_clk_s),
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.CLKFBOUT (mmcm_fb_clk_s),
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.CLKOUT0 (mmcm_clk_0_s),
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.CLKOUT1 (mmcm_clk_1_s),
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.LOCKED (mmcm_locked_s),
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.DCLK (up_clk),
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.DEN (up_drp_sel),
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.DADDR (up_drp_addr[6:0]),
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.DWE (up_drp_wr),
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.DI (up_drp_wdata),
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.DO (up_drp_rdata_s),
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.DRDY (up_drp_ready_s),
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.CLKFBOUTB (),
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.CLKOUT0B (),
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.CLKOUT1B (),
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.CLKOUT2 (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKIN2 (1'b0),
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.CLKINSEL (1'b1),
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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.CLKINSTOPPED (),
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.CLKFBSTOPPED (),
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.PWRDWN (1'b0),
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.RST (mmcm_rst));
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end
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endgenerate
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BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
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BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
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BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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