493 lines
19 KiB
Verilog
493 lines
19 KiB
Verilog
// -------------------------------------------------------------
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//
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// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerPeripheralHdlAdi.v
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// Created: 2014-09-08 14:12:09
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//
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// Generated by MATLAB 8.2 and HDL Coder 3.3
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//
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//
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// -- -------------------------------------------------------------
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// -- Rate and Clocking Details
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// -- -------------------------------------------------------------
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// Model base rate: 2e-08
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// Target subsystem base rate: 2e-08
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//
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//
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// Clock Enable Sample Time
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// -- -------------------------------------------------------------
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// ce_out_0 2e-08
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// ce_out_1 4e-05
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// -- -------------------------------------------------------------
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//
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//
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// Output Signal Clock Enable Sample Time
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// -- -------------------------------------------------------------
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// pwm_a ce_out_0 2e-08
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// pwm_b ce_out_0 2e-08
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// pwm_c ce_out_0 2e-08
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// mon_phase_voltage_a ce_out_1 4e-05
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// mon_phase_voltage_b ce_out_1 4e-05
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// mon_phase_current_a ce_out_1 4e-05
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// mon_phase_current_b ce_out_1 4e-05
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// mon_rotor_position ce_out_1 4e-05
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// mon_electrical_position ce_out_1 4e-05
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// mon_rotor_velocity ce_out_1 4e-05
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// mon_d_current ce_out_1 4e-05
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// mon_q_current ce_out_1 4e-05
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// axi_electrical_pos_err ce_out_1 4e-05
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// -- -------------------------------------------------------------
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//
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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//
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// Module: controllerPeripheralHdlAdi
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// Source Path: controllerPeripheralHdlAdi
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// Hierarchy Level: 0
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//
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// Simulink model description for controllerPeripheralHdlAdi:
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//
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// Controller Algorithm for Permanent Magnet Synchronous Machine
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//
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// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control.
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// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals.
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// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages.
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//
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// Simulink subsystem description for controllerPeripheralHdlAdi:
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//
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// Controller Algorithm for Permanent Magnet Synchronous Machine
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//
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// Specifies controller software component for Permanent Magnet Synchronous Machine (PMSM) using Field-Oriented Control.
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// The sensors bus/structure contains values returned by the Analog to Digital Converter (ADC) and quadrature encoder peripherals.
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// The controller outputs compare values used by the Pulse Width Modulators (PWMs) to generate the phase voltages.
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//
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module controllerPeripheralHdlAdi
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(
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CLK_IN,
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reset,
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clk_enable,
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adc_current1,
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adc_current2,
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encoder_a,
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encoder_b,
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encoder_index,
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axi_controller_mode,
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axi_command,
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axi_velocity_p_gain,
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axi_velocity_i_gain,
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axi_current_p_gain,
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axi_current_i_gain,
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axi_open_loop_bias,
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axi_open_loop_scalar,
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axi_encoder_zero_offset,
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ce_out_0,
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ce_out_1,
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pwm_a,
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pwm_b,
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pwm_c,
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mon_phase_voltage_a,
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mon_phase_voltage_b,
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mon_phase_current_a,
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mon_phase_current_b,
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mon_rotor_position,
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mon_electrical_position,
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mon_rotor_velocity,
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mon_d_current,
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mon_q_current,
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axi_electrical_pos_err
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);
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input CLK_IN;
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input reset;
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input clk_enable;
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input signed [17:0] adc_current1; // sfix18_En17
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input signed [17:0] adc_current2; // sfix18_En17
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input encoder_a;
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input encoder_b;
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input encoder_index;
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input [1:0] axi_controller_mode; // ufix2
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input signed [17:0] axi_command; // sfix18_En8
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input signed [17:0] axi_velocity_p_gain; // sfix18_En16
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input signed [17:0] axi_velocity_i_gain; // sfix18_En15
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input signed [17:0] axi_current_p_gain; // sfix18_En10
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input signed [17:0] axi_current_i_gain; // sfix18_En2
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input signed [17:0] axi_open_loop_bias; // sfix18_En14
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input signed [17:0] axi_open_loop_scalar; // sfix18_En16
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input signed [17:0] axi_encoder_zero_offset; // sfix18_En14
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output ce_out_0;
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output ce_out_1;
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output pwm_a;
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output pwm_b;
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output pwm_c;
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output signed [31:0] mon_phase_voltage_a; // int32
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output signed [31:0] mon_phase_voltage_b; // int32
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output signed [31:0] mon_phase_current_a; // int32
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output signed [31:0] mon_phase_current_b; // int32
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output signed [31:0] mon_rotor_position; // int32
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output signed [31:0] mon_electrical_position; // int32
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output signed [31:0] mon_rotor_velocity; // int32
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output signed [31:0] mon_d_current; // int32
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output signed [31:0] mon_q_current; // int32
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output signed [18:0] axi_electrical_pos_err; // sfix19_En14
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wire enb_1_2000_0;
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wire enb_1_2000_1;
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wire enb;
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wire enb_1_1_1;
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reg signed [17:0] Delay1_out1; // sfix18_En17
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reg signed [17:0] Delay7_out1; // sfix18_En17
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wire Rate_Transition2_out1;
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wire [15:0] Rate_Transition6_out1; // uint16
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wire [15:0] Controller_out1_0; // uint16
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wire [15:0] Controller_out1_1; // uint16
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wire [15:0] Controller_out1_2; // uint16
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wire signed [19:0] Controller_out2_0; // sfix20_En12
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wire signed [19:0] Controller_out2_1; // sfix20_En12
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wire signed [19:0] Controller_out2_2; // sfix20_En12
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wire signed [17:0] Controller_out3_0; // sfix18_En15
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wire signed [17:0] Controller_out3_1; // sfix18_En15
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wire signed [17:0] Controller_out4; // sfix18_En14
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wire signed [17:0] Controller_out5; // sfix18_En14
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wire signed [17:0] Controller_out6; // sfix18_En8
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wire signed [17:0] Controller_out7_0; // sfix18_En15
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wire signed [17:0] Controller_out7_1; // sfix18_En15
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wire signed [18:0] Controller_out8; // sfix19_En14
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reg Delay2_out1;
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reg Delay3_out1;
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reg Delay4_out1;
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wire Encoder_Peripheral_Hardware_Specification_out1;
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wire [15:0] Encoder_Peripheral_Hardware_Specification_out2; // uint16
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reg Rate_Transition2_bypass_reg; // ufix1
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reg [15:0] Rate_Transition6_bypass_reg; // ufix16
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wire [15:0] Controller_out1 [0:2]; // uint16 [3]
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reg [15:0] Rate_Transition1_out1 [0:2]; // uint16 [3]
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wire PWM_out1_0;
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wire PWM_out1_1;
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wire PWM_out1_2;
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wire [0:2] PWM_out1; // boolean [3]
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reg [0:2] Delay5_out1; // boolean [3]
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wire signed [19:0] Controller_out2 [0:2]; // sfix20_En12 [3]
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wire signed [31:0] Data_Type_Conversion_cast; // sfix32_En12
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wire signed [31:0] Data_Type_Conversion_cast_1; // sfix32_En12
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wire signed [31:0] Data_Type_Conversion_cast_2; // sfix32_En12
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wire signed [31:0] Data_Type_Conversion_out1 [0:2]; // int32 [3]
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wire signed [17:0] Controller_out3 [0:1]; // sfix18_En15 [2]
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wire signed [31:0] Data_Type_Conversion1_cast; // sfix32_En15
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wire signed [31:0] Data_Type_Conversion1_cast_1; // sfix32_En15
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wire signed [31:0] Data_Type_Conversion1_out1 [0:1]; // int32 [2]
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wire signed [31:0] Data_Type_Conversion2_out1; // int32
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wire signed [31:0] Data_Type_Conversion3_out1; // int32
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wire signed [31:0] Data_Type_Conversion4_out1; // int32
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wire signed [17:0] Controller_out7 [0:1]; // sfix18_En15 [2]
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wire signed [31:0] Data_Type_Conversion5_cast; // sfix32_En15
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wire signed [31:0] Data_Type_Conversion5_cast_1; // sfix32_En15
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wire signed [31:0] Data_Type_Conversion5_out1 [0:1]; // int32 [2]
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// Controller Peripheral HDL
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// Analog Devices Reference Framework
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//
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// Copyright 2013 The MathWorks, Inc.
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controllerPeripheralHdlAdi_tc u_controllerPeripheralHdlAdi_tc (.CLK_IN(CLK_IN),
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.reset(reset),
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.clk_enable(clk_enable),
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.enb(enb),
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.enb_1_1_1(enb_1_1_1),
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.enb_1_2000_0(enb_1_2000_0),
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.enb_1_2000_1(enb_1_2000_1)
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);
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// <Root>/Delay1
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//
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// <Root>/Mux
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always @(posedge CLK_IN)
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begin : Delay1_process
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if (reset == 1'b1) begin
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Delay1_out1 <= 18'sb000000000000000000;
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end
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else if (enb_1_2000_0) begin
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Delay1_out1 <= adc_current1;
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end
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end
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// <Root>/Delay7
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always @(posedge CLK_IN)
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begin : Delay7_process
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if (reset == 1'b1) begin
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Delay7_out1 <= 18'sb000000000000000000;
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end
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else if (enb_1_2000_0) begin
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Delay7_out1 <= adc_current2;
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end
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end
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// <Root>/Delay2
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always @(posedge CLK_IN)
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begin : Delay2_process
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if (reset == 1'b1) begin
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Delay2_out1 <= 1'b0;
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end
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else if (enb) begin
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Delay2_out1 <= encoder_a;
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end
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end
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// <Root>/Delay3
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always @(posedge CLK_IN)
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begin : Delay3_process
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if (reset == 1'b1) begin
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Delay3_out1 <= 1'b0;
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end
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else if (enb) begin
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Delay3_out1 <= encoder_b;
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end
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end
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// <Root>/Delay4
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always @(posedge CLK_IN)
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begin : Delay4_process
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if (reset == 1'b1) begin
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Delay4_out1 <= 1'b0;
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end
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else if (enb) begin
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Delay4_out1 <= encoder_index;
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end
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end
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// <Root>/Encoder_Peripheral_Hardware_Specification
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Encoder_Peripheral_Hardware_Specification u_Encoder_Peripheral_Hardware_Specification (.CLK_IN(CLK_IN),
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.reset(reset),
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.enb(enb),
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.a(Delay2_out1),
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.b(Delay3_out1),
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.index(Delay4_out1),
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.valid(Encoder_Peripheral_Hardware_Specification_out1),
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.count(Encoder_Peripheral_Hardware_Specification_out2) // uint16
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);
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// <Root>/Rate Transition2
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always @(posedge CLK_IN)
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begin : Rate_Transition2_bypass_process
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if (reset == 1'b1) begin
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Rate_Transition2_bypass_reg <= 1'b0;
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end
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else if (enb_1_2000_1) begin
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Rate_Transition2_bypass_reg <= Encoder_Peripheral_Hardware_Specification_out1;
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end
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end
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assign Rate_Transition2_out1 = (enb_1_2000_1 == 1'b1 ? Encoder_Peripheral_Hardware_Specification_out1 :
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Rate_Transition2_bypass_reg);
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// <Root>/Rate Transition6
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always @(posedge CLK_IN)
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begin : Rate_Transition6_bypass_process
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if (reset == 1'b1) begin
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Rate_Transition6_bypass_reg <= 16'b0000000000000000;
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end
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else if (enb_1_2000_1) begin
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Rate_Transition6_bypass_reg <= Encoder_Peripheral_Hardware_Specification_out2;
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end
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end
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assign Rate_Transition6_out1 = (enb_1_2000_1 == 1'b1 ? Encoder_Peripheral_Hardware_Specification_out2 :
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Rate_Transition6_bypass_reg);
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// <Root>/Controller
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controllerHdl_controllerHdl u_Controller (.CLK_IN(CLK_IN),
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.reset(reset),
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.enb_1_2000_0(enb_1_2000_0),
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.adc_current_0(Delay1_out1), // sfix18_En17
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.adc_current_1(Delay7_out1), // sfix18_En17
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.encoder_valid(Rate_Transition2_out1),
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.encoder_count(Rate_Transition6_out1), // uint16
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.controller_mode(axi_controller_mode), // ufix2
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.command(axi_command), // sfix18_En8
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.param_velocity_p_gain(axi_velocity_p_gain), // sfix18_En16
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.param_velocity_i_gain(axi_velocity_i_gain), // sfix18_En15
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.param_current_p_gain(axi_current_p_gain), // sfix18_En10
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.param_current_i_gain(axi_current_i_gain), // sfix18_En2
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.param_open_loop_bias(axi_open_loop_bias), // sfix18_En14
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.param_open_loop_scalar(axi_open_loop_scalar), // sfix18_En16
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.param_encoder_zero_offset(axi_encoder_zero_offset), // sfix18_En14
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.pwm_compare_0(Controller_out1_0), // uint16
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.pwm_compare_1(Controller_out1_1), // uint16
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.pwm_compare_2(Controller_out1_2), // uint16
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.phase_voltages_0(Controller_out2_0), // sfix20_En12
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.phase_voltages_1(Controller_out2_1), // sfix20_En12
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.phase_voltages_2(Controller_out2_2), // sfix20_En12
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.phase_currents_0(Controller_out3_0), // sfix18_En15
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.phase_currents_1(Controller_out3_1), // sfix18_En15
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.rotor_position(Controller_out4), // sfix18_En14
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.electrical_position(Controller_out5), // sfix18_En14
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.rotor_velocity(Controller_out6), // sfix18_En8
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.dq_currents_0(Controller_out7_0), // sfix18_En15
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.dq_currents_1(Controller_out7_1), // sfix18_En15
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.electrical_position_err_reg(Controller_out8) // sfix19_En14
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);
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assign Controller_out1[0] = Controller_out1_0;
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assign Controller_out1[1] = Controller_out1_1;
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assign Controller_out1[2] = Controller_out1_2;
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// <Root>/Rate Transition1
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always @(posedge CLK_IN)
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begin : Rate_Transition1_process
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if (reset == 1'b1) begin
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Rate_Transition1_out1[0] <= 16'b0000000000000000;
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Rate_Transition1_out1[1] <= 16'b0000000000000000;
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Rate_Transition1_out1[2] <= 16'b0000000000000000;
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end
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else if (enb_1_2000_0) begin
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Rate_Transition1_out1[0] <= Controller_out1[0];
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Rate_Transition1_out1[1] <= Controller_out1[1];
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Rate_Transition1_out1[2] <= Controller_out1[2];
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end
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end
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// <Root>/PWM
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PWM u_PWM (.CLK_IN(CLK_IN),
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.reset(reset),
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.enb(enb),
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.c_0(Rate_Transition1_out1[0]), // uint16
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.c_1(Rate_Transition1_out1[1]), // uint16
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.c_2(Rate_Transition1_out1[2]), // uint16
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.pwm_0(PWM_out1_0), // boolean
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.pwm_1(PWM_out1_1), // boolean
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.pwm_2(PWM_out1_2) // boolean
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);
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assign PWM_out1[0] = PWM_out1_0;
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assign PWM_out1[1] = PWM_out1_1;
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assign PWM_out1[2] = PWM_out1_2;
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// <Root>/Delay5
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always @(posedge CLK_IN)
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begin : Delay5_process
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if (reset == 1'b1) begin
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Delay5_out1[0] <= 1'b0;
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Delay5_out1[1] <= 1'b0;
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Delay5_out1[2] <= 1'b0;
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end
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else if (enb) begin
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Delay5_out1[0] <= PWM_out1[0];
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Delay5_out1[1] <= PWM_out1[1];
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Delay5_out1[2] <= PWM_out1[2];
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end
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end
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// <Root>/Demux
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assign pwm_a = Delay5_out1[0];
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assign pwm_b = Delay5_out1[1];
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assign pwm_c = Delay5_out1[2];
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assign Controller_out2[0] = Controller_out2_0;
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assign Controller_out2[1] = Controller_out2_1;
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assign Controller_out2[2] = Controller_out2_2;
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// <Root>/Data Type Conversion
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assign Data_Type_Conversion_cast = Controller_out2[0];
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assign Data_Type_Conversion_out1[0] = Data_Type_Conversion_cast;
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assign Data_Type_Conversion_cast_1 = Controller_out2[1];
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assign Data_Type_Conversion_out1[1] = Data_Type_Conversion_cast_1;
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assign Data_Type_Conversion_cast_2 = Controller_out2[2];
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assign Data_Type_Conversion_out1[2] = Data_Type_Conversion_cast_2;
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// <Root>/Selector
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assign mon_phase_voltage_a = Data_Type_Conversion_out1[0];
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// <Root>/Selector1
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assign mon_phase_voltage_b = Data_Type_Conversion_out1[1];
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assign Controller_out3[0] = Controller_out3_0;
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assign Controller_out3[1] = Controller_out3_1;
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// <Root>/Data Type Conversion1
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assign Data_Type_Conversion1_cast = Controller_out3[0];
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assign Data_Type_Conversion1_out1[0] = Data_Type_Conversion1_cast;
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assign Data_Type_Conversion1_cast_1 = Controller_out3[1];
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assign Data_Type_Conversion1_out1[1] = Data_Type_Conversion1_cast_1;
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// <Root>/Demux2
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assign mon_phase_current_a = Data_Type_Conversion1_out1[0];
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assign mon_phase_current_b = Data_Type_Conversion1_out1[1];
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// <Root>/Data Type Conversion2
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assign Data_Type_Conversion2_out1 = Controller_out4;
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assign mon_rotor_position = Data_Type_Conversion2_out1;
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// <Root>/Data Type Conversion3
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assign Data_Type_Conversion3_out1 = Controller_out5;
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assign mon_electrical_position = Data_Type_Conversion3_out1;
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// <Root>/Data Type Conversion4
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assign Data_Type_Conversion4_out1 = Controller_out6;
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assign mon_rotor_velocity = Data_Type_Conversion4_out1;
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assign Controller_out7[0] = Controller_out7_0;
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assign Controller_out7[1] = Controller_out7_1;
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// <Root>/Data Type Conversion5
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assign Data_Type_Conversion5_cast = Controller_out7[0];
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assign Data_Type_Conversion5_out1[0] = Data_Type_Conversion5_cast;
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assign Data_Type_Conversion5_cast_1 = Controller_out7[1];
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assign Data_Type_Conversion5_out1[1] = Data_Type_Conversion5_cast_1;
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// <Root>/Demux1
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assign mon_d_current = Data_Type_Conversion5_out1[0];
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assign mon_q_current = Data_Type_Conversion5_out1[1];
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assign axi_electrical_pos_err = Controller_out8;
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assign ce_out_0 = enb_1_1_1;
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assign ce_out_1 = enb_1_2000_1;
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endmodule // controllerPeripheralHdlAdi
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