45 lines
1.9 KiB
Markdown
45 lines
1.9 KiB
Markdown
# ADRV9364Z7020 SDR SOM
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This folder contains the ADRV9364Z7020 SOM projects for each of the carrier boards.
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## Board Design Files
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| Directory/File | Description |
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|-----------------------------|----------------------------------------|
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| common/adrv9364z7020_bd.tcl | ADRV9364Z7020 SOM module board design file. |
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| common/ccbob_bd.tcl | carrier, break out board design file. |
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| common/ccusb_bd.tcl | carrier, usb board design file. |
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BOB carrier design includes loopback daughtercards for connectivity testing.
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## Board Constraint Files
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| Directory/File | Description |
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|--------------------------------------|-----------------------------------------------|
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| common/adrv9364z7020_constr.xdc | ADRV9364Z7020 SOM base constraints file. |
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| common/adrv9364z7020_constr_cmos.xdc | ADRV9364Z7020 SOM CMOS mode constraints file. |
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| common/adrv9364z7020_constr_lvds.xdc | ADRV9364Z7020 SOM LVDS mode constraints file. |
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| common/ccbob_constr.xdc | carrier, break out board constraints file. |
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| common/ccbox_constr.xdc | carrier, box board constraints file. |
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| common/ccusb_constr.xdc | carrier, usb board constraints file. |
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## Building, Generating Bit Files
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[adrv9364z7020] cd ccbob_cmos
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[adrv9364z7020/ccbob_cmos] make
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The make in each carrier directory builds the corresponding project. The above example builds ADRV4CRR-BOB hardware bit files in CMOS mode.
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## Documentation
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* [HDL Design User Guide]
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* [IP User Guide]
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* [ADRV4CRR Wiki page]
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[HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl
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[IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361
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[ADRV4CRR Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr
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