92 lines
3.9 KiB
Tcl
92 lines
3.9 KiB
Tcl
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package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME axi_ad9144
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set_module_property DESCRIPTION "AXI AD9144 Interface"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_ad9144
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set_module_property ELABORATION_CALLBACK p_axi_ad9144
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL axi_ad9144
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add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
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add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
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add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
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add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
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add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
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add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
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add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
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add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
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add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
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add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
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add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
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add_fileset_file axi_ad9144_channel.v VERILOG PATH axi_ad9144_channel.v
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add_fileset_file axi_ad9144_core.v VERILOG PATH axi_ad9144_core.v
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add_fileset_file axi_ad9144_if.v VERILOG PATH axi_ad9144_if.v
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add_fileset_file axi_ad9144.v VERILOG PATH axi_ad9144.v TOP_LEVEL_FILE
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add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
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add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
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add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
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add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID TYPE INTEGER
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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add_parameter QUAD_OR_DUAL_N INTEGER 0
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set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 0
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set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N
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set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
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set_parameter_property QUAD_OR_DUAL_N UNITS None
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set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
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# axi4 slave
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
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# transceiver interface
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ad_alt_intf clock tx_clk input 1
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add_interface if_tx_data avalon_streaming source
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add_interface_port if_tx_data tx_data data output 128*(QUAD_OR_DUAL_N+1)
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add_interface_port if_tx_data tx_valid valid output 1
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add_interface_port if_tx_data tx_ready ready input 1
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set_interface_property if_tx_data associatedClock if_tx_clk
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set_interface_property if_tx_data dataBitsPerSymbol 128
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# dma interface
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ad_alt_intf clock dac_clk output 1
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for {set i 0} {$i < 4} {incr i} {
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add_interface dac_ch_${i} conduit end
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add_interface_port dac_ch_${i} dac_enable_${i} enable Output 1
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add_interface_port dac_ch_${i} dac_valid_${i} valid Output 1
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add_interface_port dac_ch_${i} dac_ddata_${i} data Input 64
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set_interface_property dac_ch_${i} associatedClock if_tx_clk
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set_interface_property dac_ch_${i} associatedReset none
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}
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ad_alt_intf signal dac_dunf input 1 unf
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proc p_axi_ad9144 {} {
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if {[get_parameter_value QUAD_OR_DUAL_N] != 1} {
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set_interface_property dac_ch_2 ENABLED false
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set_interface_property dac_ch_3 ENABLED false
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}
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}
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