259 lines
8.1 KiB
Verilog
259 lines
8.1 KiB
Verilog
// -----------------------------------------------------------------------------
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//
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
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// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
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// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// -----------------------------------------------------------------------------
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// FILE NAME : speed_detector.v
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// MODULE NAME : speed_detector
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// AUTHOR : ACostina
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// AUTHOR'S EMAIL : adrian.costina@analog.com
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// -----------------------------------------------------------------------------
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// KEYWORDS : Analog Devices, Motor Control, Speed detector
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// -----------------------------------------------------------------------------
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// PURPOSE : Detects the speed of rotation of a motor
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// -----------------------------------------------------------------------------
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// REUSE ISSUES
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// Reset Strategy :
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// Clock Domains :
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// Critical Timing :
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// Test Features :
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// Asynchronous I/F :
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// Instantiations :
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// Synthesizable (y/n) :
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// Target Device :
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// Other :
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// -----------------------------------------------------------------------------
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`timescale 1ns / 1ps
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module speed_detector
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//----------- Paramters Declarations -------------------------------------------
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#(
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parameter AVERAGE_WINDOW = 32, // Averages data on the latest samples
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parameter LOG_2_AW = 5, // Average window is 2 ^ LOG_2_AW
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parameter SAMPLE_CLK_DECIM = 10000
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)
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//----------- Ports Declarations -----------------------------------------------
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(
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input clk_i,
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input rst_i,
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input [ 2:0] position_i, // position as determined by the sensors
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output reg new_speed_o, // signals a new speed has been computed
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output reg [31:0] current_speed_o, // data bus with the current speed
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output reg [31:0] speed_o // data bus with the mediated speed
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);
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//------------------------------------------------------------------------------
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//----------- Local Parameters -------------------------------------------------
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//------------------------------------------------------------------------------
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localparam AW = LOG_2_AW - 1;
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localparam MAX_SPEED_CNT = 32'h10000;
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//State machine
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localparam RESET = 8'b00000001;
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localparam INIT = 8'b00000010;
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localparam CHANGE_POSITION = 8'b00000100;
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localparam ADD_COUNTER = 8'b00001000;
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localparam SUBSTRACT_MEM = 8'b00010000;
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localparam UPDATE_MEM = 8'b00100000;
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localparam IDLE = 8'b10000000;
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [ 2:0] position_old;
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reg [63:0] avg_register;
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reg [63:0] avg_register_stable;
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reg [31:0] cnt_period;
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reg [31:0] decimation; // register used to divide by ten the speed
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reg [31:0] cnt_period_old;
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reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM
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reg [AW:0] write_addr;
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reg [AW:0] read_addr;
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reg [31:0] sample_clk_div;
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reg [ 7:0] state;
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reg [ 7:0] next_state;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// Count ticks per position
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always @(posedge clk_i)
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begin
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if(rst_i == 1'b1)
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begin
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cnt_period <= 32'b0;
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decimation <= 32'b0;
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end
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else
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begin
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if(state != CHANGE_POSITION)
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begin
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if(decimation == 9)
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begin
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cnt_period <= cnt_period + 1;
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decimation <= 32'b0;
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end
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else
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begin
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decimation <= decimation + 1;
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end
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end
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else
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begin
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decimation <= 32'b0;
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cnt_period <= 32'b0;
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cnt_period_old <= cnt_period;
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end
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end
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end
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always @(posedge clk_i)
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begin
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if(rst_i == 1'b1)
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begin
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state <= RESET;
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end
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else
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begin
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state <= next_state;
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end
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end
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always @*
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begin
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next_state = state;
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case(state)
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RESET:
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begin
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next_state = INIT;
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end
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INIT:
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begin
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if(position_i != position_old)
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begin
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next_state = CHANGE_POSITION;
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end
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end
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CHANGE_POSITION:
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begin
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next_state = ADD_COUNTER;
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end
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ADD_COUNTER:
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begin
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next_state = SUBSTRACT_MEM;
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end
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SUBSTRACT_MEM:
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begin
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next_state = UPDATE_MEM;
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end
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UPDATE_MEM:
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begin
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next_state = IDLE;
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end
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IDLE:
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begin
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if(position_i != position_old)
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begin
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next_state = CHANGE_POSITION;
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end
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end
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endcase
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end
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always @(posedge clk_i)
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begin
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case(state)
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RESET:
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begin
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avg_register <= MAX_SPEED_CNT;
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fifo[write_addr] <= MAX_SPEED_CNT;
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end
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INIT:
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begin
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end
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CHANGE_POSITION:
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begin
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position_old <= position_i;
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end
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ADD_COUNTER:
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begin
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avg_register <= avg_register + cnt_period_old ;
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end
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SUBSTRACT_MEM:
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begin
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avg_register <= avg_register - fifo[write_addr];
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end
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UPDATE_MEM:
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begin
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fifo[write_addr] <= cnt_period_old;
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write_addr <= write_addr + 1;
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avg_register_stable <= avg_register;
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end
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IDLE:
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begin
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end
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endcase
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end
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// Stable sampling frequency of the motor speed
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always @(posedge clk_i)
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begin
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if(rst_i == 1'b1)
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begin
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sample_clk_div <= 0;
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speed_o <= 0;
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new_speed_o <= 0;
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end
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else
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begin
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if(sample_clk_div == SAMPLE_CLK_DECIM)
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begin
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sample_clk_div <= 0;
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speed_o <=(avg_register_stable >> LOG_2_AW);
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new_speed_o <= 1;
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current_speed_o <= cnt_period_old;
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end
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else
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begin
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new_speed_o <= 0;
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sample_clk_div <= sample_clk_div + 1;
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end
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end
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end
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endmodule
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