c1ba57f808
At the moment the register map fabric and DMA system memory side are clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot faster than the clock has to run. There are only a few 100 register map accesses per seconds at most and they are not on timing critical paths. The penalty from clocking them at a lower rate is negligible for the overall system performance. The maximum clock rate for the DMAs is determined by the throughput requirements. This is 200 Mbytes/s for the logic analyzer, pattern generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA. The DMA datapath width is 64-bit so the required clock rates are 25MHz and 50MHz respectively. Some headroom is required to accommodate for occasional bubble cycles on the data bus and the difference in reference clocks for the converter and processing system. The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is introduced. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| Makefile | ||
| system_bd.tcl | ||
| system_constr.xdc | ||
| system_project.tcl | ||
| system_top.v | ||