pluto_hdl_adi/projects/m2k/zed
Lars-Peter Clausen 2eaf931e07 m2k: Replace logic analyzer MMCM
The MMCM generating the logic analyzer clock unfortunately consumes a
disproportionately large amount of power compared to the rest of the
design.

Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs.
The IO PLL is running anyway so the power requirement is much lower.

For the time being this means we loose the ability to source the clock from
an external pin. But that feature is not supported by software at the
moment anyway. We'll bring it eventually when required.

This changes reduces power consumption by roughly 100mW.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
..
Makefile m2k: Reduce AXI interconnect utilization 2017-04-18 12:17:39 +02:00
system_bd.tcl M2K: initial commit 2017-01-31 16:43:40 +02:00
system_constr.xdc m2k: Replace logic analyzer MMCM 2017-04-18 12:17:39 +02:00
system_project.tcl remove processing order (no clock def dependency) 2017-02-22 16:02:08 -05:00
system_top.v m2k: Updated project to use new tx path with serdes 2017-04-18 12:17:39 +02:00