Bogdan Luncan 73af87a324 ad9081: Versal transceiver update ... - Remove 4 lane limitation - Adds support for RX or TX only instantiation Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>		2023-05-10 12:59:58 +03:00
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Makefile	library & projects: Update Makefiles	2023-01-27 11:54:05 +02:00
system_bd.tcl	Updated the makefiles to build the projects in subdirectories based on the build parameters.	2022-11-14 09:38:42 +02:00
system_constr.xdc	ad9081_fmca_ebz/zcu102: Make second sync CMOS and GPIO controllable	2022-05-11 18:09:08 +03:00
system_project.tcl	ad9081: Versal transceiver update	2023-05-10 12:59:58 +03:00
system_top.v	projects: Update .v files according to guideline	2022-06-28 18:06:56 +03:00
timing_constr.xdc	ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency	2021-02-05 15:24:15 +02:00