256 lines
7.3 KiB
Verilog
256 lines
7.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout iic_scl,
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inout iic_sda,
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inout [19:0] gpio_bd,
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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output enable,
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output txnrx,
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input clkout_in,
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output clkout_out,
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inout gpio_clksel,
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inout gpio_resetb,
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inout gpio_sync,
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inout gpio_en_agc,
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inout [ 3:0] gpio_ctl,
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inout [ 7:0] gpio_status,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso,
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output [85:0] gp_out,
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input [85:0] gp_in,
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input gt_ref_clk_p,
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input gt_ref_clk_n,
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output [ 3:0] gt_tx_p,
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output [ 3:0] gt_tx_n,
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input [ 3:0] gt_rx_p,
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input [ 3:0] gt_rx_n);
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// internal signals
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wire gt_ref_clk;
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wire [95:0] gp_out_s;
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wire [95:0] gp_in_s;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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// assignments
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assign clkout_out = clkout_in;
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assign gp_out[85:0] = gp_out_s[85:0];
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assign gp_in_s[95:86] = gp_out_s[95:86];
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assign gp_in_s[85: 0] = gp_in[85:0];
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// instantiations
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IBUFDS_GTE2 i_ibufds_gt_ref_clk (
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.CEB (1'd0),
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.I (gt_ref_clk_p),
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.IB (gt_ref_clk_n),
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.O (gt_ref_clk),
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.ODIV2 ());
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// board gpio - 31-0
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assign gpio_i[31:20] = gpio_o[31:20];
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ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
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.dio_t (gpio_t[19:0]),
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.dio_i (gpio_o[19:0]),
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.dio_o (gpio_i[19:0]),
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.dio_p (gpio_bd));
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// ad9361 gpio - 63-32
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assign gpio_i[63:52] = gpio_o[63:52];
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assign gpio_i[50:47] = gpio_o[50:47];
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ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
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.dio_t ({gpio_t[51], gpio_t[46:32]}),
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.dio_i ({gpio_o[51], gpio_o[46:32]}),
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.dio_o ({gpio_i[51], gpio_i[46:32]}),
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.dio_p ({ gpio_clksel, // 51:51
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gpio_resetb, // 46:46
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gpio_sync, // 45:45
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gpio_en_agc, // 44:44
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gpio_ctl, // 43:40
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gpio_status})); // 39:32
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// instantiations
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.enable (enable),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gp_in_0 (gp_in_s[31:0]),
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.gp_in_1 (gp_in_s[63:32]),
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.gp_in_2 (gp_in_s[95:64]),
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.gp_in_3 (32'd0),
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.gp_out_0 (gp_out_s[31:0]),
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.gp_out_1 (gp_out_s[63:32]),
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.gp_out_2 (gp_out_s[95:64]),
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.gp_out_3 (),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.gt_ref_clk (gt_ref_clk),
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.gt_rx_n (gt_rx_n),
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.gt_rx_p (gt_rx_p),
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.gt_tx_n (gt_tx_n),
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.gt_tx_p (gt_tx_p),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.otg_vbusoc (1'b0),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_15 (1'b0),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk),
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.spi0_csn_0_o (spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_miso),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_mosi),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o (),
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.tdd_sync_i (1'b0),
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.tdd_sync_o (),
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.tdd_sync_t (),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.txnrx (txnrx),
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.up_enable (gpio_o[47]),
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.up_txnrx (gpio_o[48]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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