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a10gx
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sysid_intel: Added sysid to intel projects
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2020-09-11 15:46:06 +03:00 |
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a10soc
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common/a10soc: Bridge support
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2021-02-05 10:24:59 +02:00 |
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ac701
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system_id: deployed ip
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2019-08-06 16:53:11 +03:00 |
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c5soc
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sysid_intel: Added sysid to intel projects
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2020-09-11 15:46:06 +03:00 |
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coraz7s
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cn0540: Initial commit
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2020-05-28 18:49:35 +03:00 |
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de10nano
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de10nano: Add hps_conv_usb_n signal to stabilize UART lines
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2021-01-13 15:36:45 +02:00 |
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intel
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Update Quartus Prime version from 19.3.0 to 20.1.0
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2021-03-08 11:29:33 +02:00 |
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kc705
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system_id: deployed ip
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2019-08-06 16:53:11 +03:00 |
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kcu105
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Update Vivado version to 2020.2
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2021-07-29 14:06:42 +03:00 |
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microzed
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system_id: deployed ip
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2019-08-06 16:53:11 +03:00 |
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s10soc
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common/s10soc: Input ports do not have a current strength property
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2020-09-25 12:56:14 +03:00 |
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vc707
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vc707: Fix mdio intf
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2021-01-15 13:50:53 +02:00 |
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vcu118
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Update Vivado version to 2020.2
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2021-07-29 14:06:42 +03:00 |
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xilinx
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ad_mem_asym: Add option to control cascade layout
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2021-09-15 12:27:49 +03:00 |
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zc702
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zynq:all: fix SPI clock constraint
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2019-08-09 16:39:56 +03:00 |
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zc706
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zynq:all: fix SPI clock constraint
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2019-08-09 16:39:56 +03:00 |
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zcu102
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adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition
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2021-08-20 10:46:09 +03:00 |
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zed
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zynq:all: fix SPI clock constraint
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2019-08-09 16:39:56 +03:00 |
1766b42a93