59 lines
2.5 KiB
Tcl
59 lines
2.5 KiB
Tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
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p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 256
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
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ad_connect sys_rst axi_ad9680_fifo/sys_rst
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ad_connect sys_clk axi_ad9680_fifo/sys_clk
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ad_connect ddr3 axi_ad9680_fifo/ddr3
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create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
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[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
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[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
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SEG_axi_ddr_cntrl_memaddr
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source ../common/fmcadc4_bd.tcl
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# ila
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set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc
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set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
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set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
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set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
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set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc
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ad_connect util_fmcadc4_gt/rx_rst mfifo_adc/din_rst
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ad_connect util_fmcadc4_gt/rx_out_clk mfifo_adc/din_clk
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ad_connect axi_ad9680_core_0/adc_valid_0 mfifo_adc/din_valid
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ad_connect axi_ad9680_core_0/adc_data_0 mfifo_adc/din_data_0
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ad_connect axi_ad9680_core_0/adc_data_1 mfifo_adc/din_data_1
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ad_connect axi_ad9680_core_1/adc_data_0 mfifo_adc/din_data_2
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ad_connect axi_ad9680_core_1/adc_data_1 mfifo_adc/din_data_3
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ad_connect util_fmcadc4_gt/rx_rst mfifo_adc/dout_rst
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ad_connect util_fmcadc4_gt/rx_out_clk mfifo_adc/dout_clk
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ad_connect util_fmcadc4_gt/rx_out_clk ila_adc/clk
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ad_connect mfifo_adc/dout_valid ila_adc/probe0
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ad_connect mfifo_adc/dout_data_0 ila_adc/probe1
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ad_connect mfifo_adc/dout_data_1 ila_adc/probe2
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ad_connect mfifo_adc/dout_data_2 ila_adc/probe3
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ad_connect mfifo_adc/dout_data_3 ila_adc/probe4
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