159 lines
5.9 KiB
Tcl
Executable File
159 lines
5.9 KiB
Tcl
Executable File
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adc_spi
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cn0540
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_mux
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux1
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux9
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux6
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux15
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux5
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux13
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create_bd_port -dir I adc_data_ready
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ad_ip_instance axi_iic axi_iic_cn0540
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ad_connect iic_cn0540 axi_iic_cn0540/iic
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# Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz)
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 10
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect spi_clk spi_clkgen/clk_0
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# create a SPI Engine architecture for ADC
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create_bd_cell -type hier spi_adc
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current_bd_instance /spi_adc
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type clk spi_clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I drdy
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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# DATA_WIDTH is set to 32
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH 32
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_instance axi_spi_engine axi_regmap
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ad_ip_parameter axi_regmap CONFIG.DATA_WIDTH 32
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ad_ip_parameter axi_regmap CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter axi_regmap CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH 32
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ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
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ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH 32
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ad_connect axi_regmap/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi_regmap/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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ad_connect spi_clk offload/spi_clk
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ad_connect spi_clk offload/ctrl_clk
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ad_connect spi_clk execution/clk
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ad_connect clk axi_regmap/s_axi_aclk
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ad_connect spi_clk axi_regmap/spi_clk
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ad_connect spi_clk interconnect/clk
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ad_connect axi_regmap/spi_resetn offload/spi_resetn
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ad_connect axi_regmap/spi_resetn execution/resetn
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ad_connect axi_regmap/spi_resetn interconnect/resetn
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ad_connect drdy offload/trigger
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ad_connect resetn axi_regmap/s_axi_aresetn
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ad_connect irq axi_regmap/irq
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current_bd_instance /
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ad_connect adc_data_ready spi_adc/drdy
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# dma for the ADC
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ad_ip_instance axi_dmac axi_cn0540_dma
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_cn0540_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_cn0540_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_cn0540_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_cn0540_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter axi_cn0540_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect $sys_cpu_clk spi_adc/clk
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ad_connect $sys_cpu_resetn spi_adc/resetn
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ad_connect $sys_cpu_resetn axi_cn0540_dma/m_dest_axi_aresetn
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ad_connect spi_adc/m_spi adc_spi
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ad_connect spi_clk spi_adc/spi_clk
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ad_connect axi_cn0540_dma/s_axis spi_adc/M_AXIS_SAMPLE
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# Xilinx's XADC
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ad_ip_instance xadc_wiz xadc_in
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ad_ip_parameter xadc_in CONFIG.XADC_STARUP_SELECTION channel_sequencer
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ad_ip_parameter xadc_in CONFIG.SEQUENCER_MODE Continuous
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VP_VN true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP5_VAUXN5 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP13_VAUXN13 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP15_VAUXN15 true
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ad_ip_parameter xadc_in CONFIG.ENABLE_VCCDDRO_ALARM false
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ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPAUX_ALARM false
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ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPINT_ALARM false
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ad_ip_parameter xadc_in CONFIG.EXTERNAL_MUX_CHANNEL VP_VN
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ad_ip_parameter xadc_in CONFIG.OT_ALARM false
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ad_ip_parameter xadc_in CONFIG.SINGLE_CHANNEL_SELECTION TEMPERATURE
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ad_ip_parameter xadc_in CONFIG.USER_TEMP_ALARM false
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ad_ip_parameter xadc_in CONFIG.VCCAUX_ALARM false
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ad_ip_parameter xadc_in CONFIG.VCCINT_ALARM false
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ad_connect xadc_in/Vp_Vn xadc_mux
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ad_connect xadc_in/Vaux1 xadc_vaux1
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ad_connect xadc_in/Vaux5 xadc_vaux5
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ad_connect xadc_in/Vaux6 xadc_vaux6
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ad_connect xadc_in/Vaux9 xadc_vaux9
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ad_connect xadc_in/Vaux13 xadc_vaux13
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ad_connect xadc_in/Vaux15 xadc_vaux15
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# AXI address definitions
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ad_cpu_interconnect 0x44a00000 spi_adc/axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_cn0540_dma
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ad_cpu_interconnect 0x44a40000 axi_iic_cn0540
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ad_cpu_interconnect 0x44a50000 xadc_in
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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ad_connect spi_clk axi_cn0540_dma/s_axis_aclk
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# interrupts
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ad_cpu_interrupt "ps-13" "mb-13" axi_cn0540_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" axi_iic_cn0540/iic2intc_irpt
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ad_cpu_interrupt "ps-11" "mb-11" spi_adc/irq
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# memory interconnects
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ad_mem_hp0_interconnect $sys_cpu_clk axi_cn0540_dma/m_dest_axi
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