284 lines
8.2 KiB
Tcl
284 lines
8.2 KiB
Tcl
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variable p_board
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variable p_device
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variable sys_zynq
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variable p_prcfg_init
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variable p_prcfg_list
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variable p_prcfg_status
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if {![info exists REQUIRED_VIVADO_VERSION]} {
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set REQUIRED_VIVADO_VERSION "2015.4.2"
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}
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if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
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set IGNORE_VERSION_CHECK 1
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} elseif {![info exists IGNORE_VERSION_CHECK]} {
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set IGNORE_VERSION_CHECK 0
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}
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proc adi_project_create {project_name {mode 0}} {
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global ad_hdl_dir
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global ad_phdl_dir
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global p_board
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global p_device
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global sys_zynq
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global REQUIRED_VIVADO_VERSION
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global IGNORE_VERSION_CHECK
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set p_device "none"
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set p_board "none"
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set sys_zynq 0
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if [regexp "_ac701$" $project_name] {
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set p_device "xc7a200tfbg676-2"
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set p_board "xilinx.com:ac701:part0:1.0"
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set sys_zynq 0
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}
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if [regexp "_kc705$" $project_name] {
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set p_device "xc7k325tffg900-2"
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set p_board "xilinx.com:kc705:part0:1.1"
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set sys_zynq 0
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}
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if [regexp "_vc707$" $project_name] {
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set p_device "xc7vx485tffg1761-2"
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set p_board "xilinx.com:vc707:part0:1.1"
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set sys_zynq 0
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}
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if [regexp "_kcu105$" $project_name] {
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set p_device "xcku040-ffva1156-2-e"
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set p_board "xilinx.com:kcu105:part0:1.0"
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set sys_zynq 0
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}
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if [regexp "_zed$" $project_name] {
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set p_device "xc7z020clg484-1"
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set p_board "em.avnet.com:zed:part0:1.3"
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set sys_zynq 1
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}
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if [regexp "_zc702$" $project_name] {
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set p_device "xc7z020clg484-1"
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set p_board "xilinx.com:zc702:part0:1.2"
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set sys_zynq 1
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}
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if [regexp "_zc706$" $project_name] {
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set p_device "xc7z045ffg900-2"
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set p_board "xilinx.com:zc706:part0:1.2"
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set sys_zynq 1
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}
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if [regexp "_mitx045$" $project_name] {
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set p_device "xc7z045ffg900-2"
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set p_board "not-applicable"
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set sys_zynq 1
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}
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if [regexp "_pzsdr$" $project_name] {
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set p_device "xc7z035ifbg676-2L"
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set p_board "not-applicable"
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set sys_zynq 1
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}
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if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} {
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return -code error [format "ERROR: This project requires Vivado %s." $REQUIRED_VIVADO_VERSION]
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}
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if {$mode == 0} {
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set project_system_dir "./$project_name.srcs/sources_1/bd/system"
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create_project $project_name . -part $p_device -force
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} else {
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set project_system_dir ".srcs/sources_1/bd/system"
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create_project -in_memory -part $p_device
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}
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if {$mode == 1} {
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file mkdir $project_name.data
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}
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if {$p_board ne "not-applicable"} {
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set_property board_part $p_board [current_project]
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}
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set lib_dirs $ad_hdl_dir/library
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if {$ad_hdl_dir ne $ad_phdl_dir} {
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lappend lib_dirs $ad_phdl_dir/library
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}
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set_property ip_repo_paths $lib_dirs [current_fileset]
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update_ip_catalog
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set_msg_config -id {BD 41-1348} -new_severity info
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set_msg_config -id {BD 41-1343} -new_severity info
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set_msg_config -id {BD 41-1306} -new_severity info
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set_msg_config -id {IP_Flow 19-1687} -new_severity info
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set_msg_config -id {filemgmt 20-1763} -new_severity info
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set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity error
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create_bd_design "system"
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source system_bd.tcl
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regenerate_bd_layout
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save_bd_design
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validate_bd_design
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generate_target {synthesis implementation} [get_files $project_system_dir/system.bd]
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make_wrapper -files [get_files $project_system_dir/system.bd] -top
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if {$mode == 0} {
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import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
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} else {
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write_hwdef -file "$project_name.data/$project_name.hwdef"
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}
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}
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proc adi_project_files {project_name project_files} {
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global ad_hdl_dir
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global ad_phdl_dir
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add_files -norecurse -fileset sources_1 $project_files
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set_property top system_top [current_fileset]
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}
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proc adi_project_run {project_name} {
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global ad_hdl_dir
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global ad_phdl_dir
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global p_board
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set project_system_dir "./$project_name.srcs/sources_1/bd/system"
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set_property constrs_type XDC [current_fileset -constrset]
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launch_runs synth_1
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wait_on_run synth_1
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open_run synth_1
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report_timing_summary -file timing_synth.log
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set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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set_property STRATEGY "Performance_Explore" [get_runs impl_1]
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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open_run impl_1
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report_timing_summary -file timing_impl.log
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file mkdir $project_name.sdk
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if [expr [get_property SLACK [get_timing_paths]] < 0] {
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file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_bad_timing.hdf
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} else {
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file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf
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}
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if [expr [get_property SLACK [get_timing_paths]] < 0] {
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return -code error [format "ERROR: Timing Constraints NOT met!"]
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}
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}
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proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
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global p_device
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set p_prefix "$project_name.data/$project_name"
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if {$prcfg_name eq ""} {
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read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
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read_verilog $hdl_files
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read_xdc $xdc_files
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synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
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write_checkpoint -force $p_prefix.synth.dcp
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close_project
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} else {
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create_project -in_memory -part $p_device
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read_verilog $hdl_files
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synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
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write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
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close_project
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}
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}
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proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
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global p_device
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global p_prcfg_init
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global p_prcfg_list
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global p_prcfg_status
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set p_prefix "$project_name.data/$project_name"
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if {$prcfg_name eq "default"} {
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set p_prcfg_status 0
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set p_prcfg_list ""
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set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
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file mkdir $project_name.sdk
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}
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if {$prcfg_name eq "default"} {
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open_checkpoint $p_prefix.synth.dcp -part $p_device
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read_xdc $xdc_files
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read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
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set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
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opt_design > $p_prefix.${prcfg_name}_opt.rds
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write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
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place_design > $p_prefix.${prcfg_name}_place.rds
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route_design > $p_prefix.${prcfg_name}_route.rds
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} else {
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open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
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lock_design -level routing
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read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
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read_xdc $xdc_files
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opt_design > $p_prefix.${prcfg_name}_opt.rds
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place_design > $p_prefix.${prcfg_name}_place.rds
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route_design > $p_prefix.${prcfg_name}_route.rds
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}
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write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
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report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
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report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
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if [expr [get_property SLACK [get_timing_paths]] < 0] {
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set p_prcfg_status 1
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puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
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}
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write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
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update_design -cell i_prcfg -black_box
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write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
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open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
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write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
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write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
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file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
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if {$prcfg_name ne "default"} {
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lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
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}
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if {$prcfg_name eq "default"} {
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file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
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}
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}
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proc adi_project_verify {project_name} {
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global p_prcfg_init
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global p_prcfg_list
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global p_prcfg_status
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set p_prefix "$project_name.data/$project_name"
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pr_verify -full_check -initial $p_prcfg_init \
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-additional $p_prcfg_list \
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-file $p_prefix.prcfg_verify.log
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if {$p_prcfg_status == 1} {
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return -code error [format "ERROR: Timing Constraints NOT met!"]
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}
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}
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