151 lines
5.4 KiB
Verilog
151 lines
5.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module fmcjesdadc1_spi (
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// master clock
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sys_clk,
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// 4-wire spi interface
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spi4_csn,
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spi4_clk,
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spi4_mosi,
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spi4_miso,
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// 3-wire spi interface
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spi3_csn,
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spi3_clk,
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spi3_sdio);
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// parameters
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localparam FMC27X_CPLD = 8'h00;
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localparam FMC27X_AD9517 = 8'h84;
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localparam FMC27X_AD9250_0 = 8'h80;
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localparam FMC27X_AD9250_1 = 8'h81;
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localparam FMC27X_AD9129_0 = 8'h82;
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localparam FMC27X_AD9129_1 = 8'h83;
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// master clock
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input sys_clk;
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// 4-wire spi interface
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input spi4_csn;
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input spi4_clk;
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input spi4_mosi;
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output spi4_miso;
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// 3-wire spi interface
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output spi3_csn;
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output spi3_clk;
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inout spi3_sdio;
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// internal registers
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reg spi4_clk_d = 'd0;
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reg spi4_csn_d = 'd0;
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reg [ 5:0] spi4_clkcnt = 'd0;
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reg [ 6:0] spi4_bitcnt = 'd0;
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reg [ 7:0] spi4_devid = 'd0;
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reg spi4_rwn = 'd0;
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reg spi3_enable = 'd0;
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// pass through most of the stuff (no need to change clock or miso or mosi)
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assign spi4_miso = spi3_sdio;
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assign spi3_csn = spi4_csn;
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assign spi3_clk = spi4_clk;
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assign spi3_sdio = ((spi4_csn == 1'b0) && (spi3_enable == 1'b1)) ? 1'bz : spi4_mosi;
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// the spi4 format is a preamble that selects a particular device, so all we need
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// to do is collect the first 8 bits, then control the tristate based on the
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// device's address and data widths. the details of the spi formats can be found
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// in the data sheet of the devices.
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always @(posedge sys_clk) begin
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spi4_clk_d <= spi4_clk;
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spi4_csn_d <= spi4_csn;
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if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin
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spi4_clkcnt <= 6'd0;
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end else begin
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spi4_clkcnt <= spi4_clkcnt + 1'b1;
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end
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if ((spi4_csn == 1'b1) && (spi4_csn_d == 1'b0)) begin
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spi4_bitcnt <= 7'd0;
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spi4_devid <= 8'd0;
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spi4_rwn <= 1'd0;
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end else if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin
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spi4_bitcnt <= spi4_bitcnt + 1'b1;
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if (spi4_bitcnt < 8) begin
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spi4_devid <= {spi4_devid[6:0], spi4_mosi};
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end
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if (spi4_bitcnt == 8) begin
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spi4_rwn <= spi4_mosi;
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end
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end
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if (spi4_csn == 1'b0) begin
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if ((spi4_devid == FMC27X_CPLD) || (spi4_devid == FMC27X_AD9129_0) ||
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(spi4_devid == FMC27X_AD9129_1)) begin
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if ((spi4_bitcnt == 16) && (spi4_clkcnt == 8)) begin
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spi3_enable <= spi4_rwn;
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end
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end else if ((spi4_devid == FMC27X_AD9517) || (spi4_devid == FMC27X_AD9250_0) ||
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(spi4_devid == FMC27X_AD9250_1)) begin
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if ((spi4_bitcnt == 24) && (spi4_clkcnt == 8)) begin
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spi3_enable <= spi4_rwn;
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end
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end
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end else begin
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spi3_enable <= 1'b0;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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