89 lines
2.6 KiB
Verilog
89 lines
2.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module __ad_cmos_out__ #(
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parameter DEVICE_TYPE = 0,
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parameter IODELAY_ENABLE = 0,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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// data interface
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input tx_clk,
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input tx_data_p,
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input tx_data_n,
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output tx_data_out,
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// delay-data interface
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// local parameter
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localparam ARRIA10 = 0;
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localparam CYCLONE5 = 1;
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// defaults
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assign up_drdata = 5'd0;
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assign delay_locked = 1'b1;
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// instantiations
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generate
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if (DEVICE_TYPE == ARRIA10) begin
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__ad_cmos_out_1__ i_tx_data_oddr (
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.clk_export (tx_clk),
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.din_export ({tx_data_p, tx_data_n}),
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.pad_out_export (tx_data_out));
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end
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endgenerate
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generate
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if (DEVICE_TYPE == CYCLONE5) begin
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ad_cmos_out_core_c5 i_tx_data_oddr (
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.clk (tx_clk),
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.din ({tx_data_p, tx_data_n}),
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.pad_out (tx_data_out));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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