127 lines
3.8 KiB
Verilog
127 lines
3.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module __ad_serdes_out__ #(
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parameter DEVICE_TYPE = 0,
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parameter DDR_OR_SDR_N = 1,
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parameter SERDES_FACTOR = 8,
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parameter DATA_WIDTH = 16) (
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// reset and clocks
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input rst,
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input clk,
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input div_clk,
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input loaden,
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// data interface
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input [(DATA_WIDTH-1):0] data_s0,
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input [(DATA_WIDTH-1):0] data_s1,
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input [(DATA_WIDTH-1):0] data_s2,
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input [(DATA_WIDTH-1):0] data_s3,
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input [(DATA_WIDTH-1):0] data_s4,
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input [(DATA_WIDTH-1):0] data_s5,
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input [(DATA_WIDTH-1):0] data_s6,
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input [(DATA_WIDTH-1):0] data_s7,
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output [(DATA_WIDTH-1):0] data_out_p,
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output [(DATA_WIDTH-1):0] data_out_n);
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// local parameter
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localparam ARRIA10 = 0;
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localparam CYCLONE5 = 1;
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// internal signals
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wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)];
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wire [(SERDES_FACTOR-1):0] data_in_s[0:(DATA_WIDTH-1)];
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// defaults
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assign data_out_n = 'd0;
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// instantiations
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genvar n;
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genvar i;
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generate
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if (SERDES_FACTOR == 8) begin
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assign data_samples_s[7] = data_s7;
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assign data_samples_s[6] = data_s6;
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assign data_samples_s[5] = data_s5;
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assign data_samples_s[4] = data_s4;
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end
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endgenerate
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assign data_samples_s[3] = data_s3;
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assign data_samples_s[2] = data_s2;
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assign data_samples_s[1] = data_s1;
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assign data_samples_s[0] = data_s0;
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generate
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
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for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
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assign data_in_s[n][((SERDES_FACTOR-1)-i)] = data_samples_s[i][n];
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end
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end
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endgenerate
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generate
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
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if (DEVICE_TYPE == CYCLONE5) begin
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ad_serdes_out_core_c5 #(
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.SERDES_FACTOR (SERDES_FACTOR))
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i_core (
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.clk (clk),
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.div_clk (div_clk),
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.enable (loaden),
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.data_out (data_out_p[n]),
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.data (data_in_s[n]));
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end
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if (DEVICE_TYPE == ARRIA10) begin
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__ad_serdes_out_1__ i_core (
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.clk_export (clk),
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.div_clk_export (div_clk),
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.loaden_export (loaden),
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.data_out_export (data_out_p[n]),
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.data_s_export (data_in_s[n]));
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end
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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